forked from OSchip/llvm-project
[ARM] make vminnm/vmaxnm work with ?le, ?ge and no-nans-fp-math
Because -menable-no-nans causes fcmp conditions to be rewritten without 'o' or 'u' the recognition code in needs to cope. Also extended it to handle 'le' and 'ge. Differential Revision: http://reviews.llvm.org/D8725 llvm-svn: 234421
This commit is contained in:
Scott Douglass
parent
71df405895
commit
7ad7792088
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@ -3504,25 +3504,34 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
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ARMCC::CondCodes CondCode, CondCode2;
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FPCCToARMCC(CC, CondCode, CondCode2);
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// Try to generate VSEL on ARMv8.
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// Try to generate VMAXNM/VMINNM on ARMv8.
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if (Subtarget->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 ||
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TrueVal.getValueType() == MVT::f64)) {
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// We can select VMAXNM/VMINNM from a compare followed by a select with the
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// We can use VMAXNM/VMINNM for a compare followed by a select with the
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// same operands, as follows:
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// c = fcmp [ogt, olt, ugt, ult] a, b
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// c = fcmp [?gt, ?ge, ?lt, ?le] a, b
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// select c, a, b
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// We only do this in unsafe-fp-math, because signed zeros and NaNs are
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// handled differently than the original code sequence.
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// In NoNaNsFPMath the CC will have been changed from, e.g., 'ogt' to 'gt'.
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// We only do this transformation in UnsafeFPMath and for no-NaNs
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// comparisons, because signed zeros and NaNs are handled differently than
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// the original code sequence.
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// FIXME: There are more cases that can be transformed even with NaNs,
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// signed zeroes and safe math. E.g. in the following, the result will be
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// FalseVal if a is a NaN or -0./0. and that's what vmaxnm will give, too.
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// c = fcmp ogt, a, 0. ; select c, a, 0. => vmaxnm a, 0.
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// FIXME: There is similar code that allows some extensions in
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// AArch64TargetLowering::LowerSELECT_CC that should be shared with this
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// code.
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if (getTargetMachine().Options.UnsafeFPMath) {
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if (LHS == TrueVal && RHS == FalseVal) {
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if (CC == ISD::SETOGT || CC == ISD::SETUGT)
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if (CC == ISD::SETGT || CC == ISD::SETGE)
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return DAG.getNode(ARMISD::VMAXNM, dl, VT, TrueVal, FalseVal);
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if (CC == ISD::SETOLT || CC == ISD::SETULT)
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if (CC == ISD::SETLT || CC == ISD::SETLE)
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return DAG.getNode(ARMISD::VMINNM, dl, VT, TrueVal, FalseVal);
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} else if (LHS == FalseVal && RHS == TrueVal) {
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if (CC == ISD::SETOLT || CC == ISD::SETULT)
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if (CC == ISD::SETLT || CC == ISD::SETLE)
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return DAG.getNode(ARMISD::VMAXNM, dl, VT, TrueVal, FalseVal);
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if (CC == ISD::SETOGT || CC == ISD::SETUGT)
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if (CC == ISD::SETGT || CC == ISD::SETGE)
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return DAG.getNode(ARMISD::VMINNM, dl, VT, TrueVal, FalseVal);
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}
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}
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@ -1,5 +1,8 @@
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; RUN: llc < %s -mtriple armv8 -mattr=+neon | FileCheck %s
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; RUN: llc < %s -mtriple armv8 -mattr=+neon,+fp-armv8 -enable-unsafe-fp-math | FileCheck %s --check-prefix=CHECK-FAST
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; RUN: llc < %s -mtriple armv8 -mattr=+neon,+fp-armv8 | FileCheck %s
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; RUN: llc < %s -mtriple armv8 -mattr=+neon,+fp-armv8 \
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; RUN: -enable-no-nans-fp-math -enable-unsafe-fp-math | FileCheck %s --check-prefix=CHECK-FAST
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; vectors
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define <4 x float> @vmaxnmq(<4 x float>* %A, <4 x float>* %B) nounwind {
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; CHECK-LABEL: vmaxnmq:
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@ -37,6 +40,8 @@ define <2 x float> @vminnmd(<2 x float>* %A, <2 x float>* %B) nounwind {
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ret <2 x float> %tmp3
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}
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; scalars
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define float @fp-armv8_vminnm_o(float %a, float %b) {
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; CHECK-FAST-LABEL: "fp-armv8_vminnm_o":
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; CHECK-FAST-NOT: vcmp
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@ -48,6 +53,17 @@ define float @fp-armv8_vminnm_o(float %a, float %b) {
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ret float %cond
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}
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define double @fp-armv8_vminnm_ole(double %a, double %b) {
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; CHECK-FAST-LABEL: "fp-armv8_vminnm_ole":
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; CHECK-FAST-NOT: vcmp
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; CHECK-FAST: vminnm.f64
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; CHECK-LABEL: "fp-armv8_vminnm_ole":
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; CHECK-NOT: vminnm.f64
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%cmp = fcmp ole double %a, %b
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%cond = select i1 %cmp, double %a, double %b
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ret double %cond
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}
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define float @fp-armv8_vminnm_o_rev(float %a, float %b) {
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; CHECK-FAST-LABEL: "fp-armv8_vminnm_o_rev":
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; CHECK-FAST-NOT: vcmp
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@ -59,6 +75,17 @@ define float @fp-armv8_vminnm_o_rev(float %a, float %b) {
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ret float %cond
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}
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define double @fp-armv8_vminnm_oge_rev(double %a, double %b) {
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; CHECK-FAST-LABEL: "fp-armv8_vminnm_oge_rev":
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; CHECK-FAST-NOT: vcmp
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; CHECK-FAST: vminnm.f64
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; CHECK-LABEL: "fp-armv8_vminnm_oge_rev":
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; CHECK-NOT: vminnm.f64
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%cmp = fcmp oge double %a, %b
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%cond = select i1 %cmp, double %b, double %a
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ret double %cond
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}
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define float @fp-armv8_vminnm_u(float %a, float %b) {
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; CHECK-FAST-LABEL: "fp-armv8_vminnm_u":
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; CHECK-FAST-NOT: vcmp
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@ -70,6 +97,17 @@ define float @fp-armv8_vminnm_u(float %a, float %b) {
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ret float %cond
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}
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define float @fp-armv8_vminnm_ule(float %a, float %b) {
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; CHECK-FAST-LABEL: "fp-armv8_vminnm_ule":
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; CHECK-FAST-NOT: vcmp
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; CHECK-FAST: vminnm.f32
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; CHECK-LABEL: "fp-armv8_vminnm_ule":
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; CHECK-NOT: vminnm.f32
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%cmp = fcmp ule float %a, %b
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%cond = select i1 %cmp, float %a, float %b
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ret float %cond
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}
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define float @fp-armv8_vminnm_u_rev(float %a, float %b) {
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; CHECK-FAST-LABEL: "fp-armv8_vminnm_u_rev":
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; CHECK-FAST-NOT: vcmp
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@ -81,6 +119,17 @@ define float @fp-armv8_vminnm_u_rev(float %a, float %b) {
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ret float %cond
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}
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define double @fp-armv8_vminnm_uge_rev(double %a, double %b) {
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; CHECK-FAST-LABEL: "fp-armv8_vminnm_uge_rev":
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; CHECK-FAST-NOT: vcmp
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; CHECK-FAST: vminnm.f64
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; CHECK-LABEL: "fp-armv8_vminnm_uge_rev":
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; CHECK-NOT: vminnm.f64
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%cmp = fcmp uge double %a, %b
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%cond = select i1 %cmp, double %b, double %a
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ret double %cond
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}
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define float @fp-armv8_vmaxnm_o(float %a, float %b) {
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; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_o":
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; CHECK-FAST-NOT: vcmp
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@ -92,6 +141,17 @@ define float @fp-armv8_vmaxnm_o(float %a, float %b) {
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ret float %cond
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}
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define float @fp-armv8_vmaxnm_oge(float %a, float %b) {
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; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_oge":
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; CHECK-FAST-NOT: vcmp
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; CHECK-FAST: vmaxnm.f32
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; CHECK-LABEL: "fp-armv8_vmaxnm_oge":
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; CHECK-NOT: vmaxnm.f32
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%cmp = fcmp oge float %a, %b
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%cond = select i1 %cmp, float %a, float %b
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ret float %cond
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}
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define float @fp-armv8_vmaxnm_o_rev(float %a, float %b) {
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; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_o_rev":
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; CHECK-FAST-NOT: vcmp
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@ -103,6 +163,17 @@ define float @fp-armv8_vmaxnm_o_rev(float %a, float %b) {
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ret float %cond
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}
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define float @fp-armv8_vmaxnm_ole_rev(float %a, float %b) {
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; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_ole_rev":
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; CHECK-FAST-NOT: vcmp
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; CHECK-FAST: vmaxnm.f32
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; CHECK-LABEL: "fp-armv8_vmaxnm_ole_rev":
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; CHECK-NOT: vmaxnm.f32
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%cmp = fcmp ole float %a, %b
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%cond = select i1 %cmp, float %b, float %a
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ret float %cond
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}
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define float @fp-armv8_vmaxnm_u(float %a, float %b) {
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; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_u":
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; CHECK-FAST-NOT: vcmp
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@ -114,6 +185,17 @@ define float @fp-armv8_vmaxnm_u(float %a, float %b) {
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ret float %cond
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}
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define float @fp-armv8_vmaxnm_uge(float %a, float %b) {
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; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_uge":
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; CHECK-FAST-NOT: vcmp
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; CHECK-FAST: vmaxnm.f32
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; CHECK-LABEL: "fp-armv8_vmaxnm_uge":
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; CHECK-NOT: vmaxnm.f32
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%cmp = fcmp uge float %a, %b
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%cond = select i1 %cmp, float %a, float %b
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ret float %cond
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}
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define float @fp-armv8_vmaxnm_u_rev(float %a, float %b) {
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; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_u_rev":
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; CHECK-FAST-NOT: vcmp
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@ -125,6 +207,17 @@ define float @fp-armv8_vmaxnm_u_rev(float %a, float %b) {
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ret float %cond
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}
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define double @fp-armv8_vmaxnm_ule_rev(double %a, double %b) {
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; CHECK-FAST-LABEL: "fp-armv8_vmaxnm_ule_rev":
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; CHECK-FAST-NOT: vcmp
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; CHECK-FAST: vmaxnm.f64
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; CHECK-LABEL: "fp-armv8_vmaxnm_ule_rev":
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; CHECK-NOT: vmaxnm.f64
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%cmp = fcmp ule double %a, %b
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%cond = select i1 %cmp, double %b, double %a
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ret double %cond
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}
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declare <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float>, <4 x float>) nounwind readnone
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declare <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float>, <2 x float>) nounwind readnone
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