maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

Added support for reporting operand token ranges 

to the ARM AsmParser.

llvm-svn: 100232
This commit is contained in:
Sean Callanan 2010-04-02 22:27:05 +00:00
parent 2ef63183a5
commit 7ad0ad0b9a
1 changed files with 151 additions and 71 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

220
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -18,6 +18,7 @@
#include "llvm/Target/TargetAsmParser.h" #include "llvm/Target/TargetAsmParser.h"
#include "llvm/Support/Compiler.h" #include "llvm/Support/Compiler.h"
#include "llvm/Support/SourceMgr.h" #include "llvm/Support/SourceMgr.h"
#include "llvm/ADT/OwningPtr.h"
#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Twine.h" #include "llvm/ADT/Twine.h"
using namespace llvm; using namespace llvm;
@ -46,11 +47,11 @@ private:
bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); } bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
bool MaybeParseRegister(ARMOperand &Op, bool ParseWriteBack); bool MaybeParseRegister(OwningPtr<ARMOperand> &Op, bool ParseWriteBack);
bool ParseRegisterList(ARMOperand &Op); bool ParseRegisterList(OwningPtr<ARMOperand> &Op);
bool ParseMemory(ARMOperand &Op); bool ParseMemory(OwningPtr<ARMOperand> &Op);
bool ParseMemoryOffsetReg(bool &Negative, bool ParseMemoryOffsetReg(bool &Negative,
bool &OffsetRegShifted, bool &OffsetRegShifted,
@ -58,11 +59,12 @@ private:
const MCExpr *&ShiftAmount, const MCExpr *&ShiftAmount,
const MCExpr *&Offset, const MCExpr *&Offset,
bool &OffsetIsReg, bool &OffsetIsReg,
int &OffsetRegNum); int &OffsetRegNum,
SMLoc &E);
bool ParseShift(enum ShiftType &St, const MCExpr *&ShiftAmount); bool ParseShift(enum ShiftType &St, const MCExpr *&ShiftAmount, SMLoc &E);
bool ParseOperand(ARMOperand &Op); bool ParseOperand(OwningPtr<ARMOperand> &Op);
bool ParseDirectiveWord(unsigned Size, SMLoc L); bool ParseDirectiveWord(unsigned Size, SMLoc L);
@ -104,13 +106,17 @@ public:
/// ARMOperand - Instances of this class represent a parsed ARM machine /// ARMOperand - Instances of this class represent a parsed ARM machine
/// instruction. /// instruction.
struct ARMOperand : public MCParsedAsmOperand { struct ARMOperand : public MCParsedAsmOperand {
enum { private:
ARMOperand() {}
public:
enum KindTy {
Token, Token,
Register, Register,
Immediate, Immediate,
Memory Memory
} Kind; } Kind;
SMLoc StartLoc, EndLoc;
union { union {
struct { struct {
@ -145,6 +151,34 @@ struct ARMOperand : public MCParsedAsmOperand {
}; };
ARMOperand(KindTy K, SMLoc S, SMLoc E)
: Kind(K), StartLoc(S), EndLoc(E) {}
ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
Kind = o.Kind;
StartLoc = o.StartLoc;
EndLoc = o.EndLoc;
switch (Kind) {
case Token:
Tok = o.Tok;
break;
case Register:
Reg = o.Reg;
break;
case Immediate:
Imm = o.Imm;
break;
case Memory:
Mem = o.Mem;
break;
}
}
/// getStartLoc - Get the location of the first token of this operand.
SMLoc getStartLoc() const { return StartLoc; }
/// getEndLoc - Get the location of the last token of this operand.
SMLoc getEndLoc() const { return EndLoc; }
StringRef getToken() const { StringRef getToken() const {
assert(Kind == Token && "Invalid access!"); assert(Kind == Token && "Invalid access!");
return StringRef(Tok.Data, Tok.Length); return StringRef(Tok.Data, Tok.Length);
@ -169,48 +203,60 @@ struct ARMOperand : public MCParsedAsmOperand {
Inst.addOperand(MCOperand::CreateReg(getReg())); Inst.addOperand(MCOperand::CreateReg(getReg()));
} }
static ARMOperand CreateToken(StringRef Str) { static void CreateToken(OwningPtr<ARMOperand> &Op, StringRef Str,
ARMOperand Res; SMLoc S) {
Res.Kind = Token; Op.reset(new ARMOperand);
Res.Tok.Data = Str.data(); Op->Kind = Token;
Res.Tok.Length = Str.size(); Op->Tok.Data = Str.data();
return Res; Op->Tok.Length = Str.size();
Op->StartLoc = S;
Op->EndLoc = S;
} }
static ARMOperand CreateReg(unsigned RegNum, bool Writeback) { static void CreateReg(OwningPtr<ARMOperand> &Op, unsigned RegNum,
ARMOperand Res; bool Writeback, SMLoc S, SMLoc E) {
Res.Kind = Register; Op.reset(new ARMOperand);
Res.Reg.RegNum = RegNum; Op->Kind = Register;
Res.Reg.Writeback = Writeback; Op->Reg.RegNum = RegNum;
return Res; Op->Reg.Writeback = Writeback;
Op->StartLoc = S;
Op->EndLoc = E;
} }
static ARMOperand CreateImm(const MCExpr *Val) { static void CreateImm(OwningPtr<ARMOperand> &Op, const MCExpr *Val,
ARMOperand Res; SMLoc S, SMLoc E) {
Res.Kind = Immediate; Op.reset(new ARMOperand);
Res.Imm.Val = Val; Op->Kind = Immediate;
return Res; Op->Imm.Val = Val;
Op->StartLoc = S;
Op->EndLoc = E;
} }
static ARMOperand CreateMem(unsigned BaseRegNum, bool OffsetIsReg, static void CreateMem(OwningPtr<ARMOperand> &Op,
const MCExpr *Offset, unsigned OffsetRegNum, unsigned BaseRegNum, bool OffsetIsReg,
bool OffsetRegShifted, enum ShiftType ShiftType, const MCExpr *Offset, unsigned OffsetRegNum,
const MCExpr *ShiftAmount, bool Preindexed, bool OffsetRegShifted, enum ShiftType ShiftType,
bool Postindexed, bool Negative, bool Writeback) { const MCExpr *ShiftAmount, bool Preindexed,
ARMOperand Res; bool Postindexed, bool Negative, bool Writeback,
Res.Kind = Memory; SMLoc S, SMLoc E) {
Res.Mem.BaseRegNum = BaseRegNum; Op.reset(new ARMOperand);
Res.Mem.OffsetIsReg = OffsetIsReg; Op->Kind = Memory;
Res.Mem.Offset = Offset; Op->Mem.BaseRegNum = BaseRegNum;
Res.Mem.OffsetRegNum = OffsetRegNum; Op->Mem.OffsetIsReg = OffsetIsReg;
Res.Mem.OffsetRegShifted = OffsetRegShifted; Op->Mem.Offset = Offset;
Res.Mem.ShiftType = ShiftType; Op->Mem.OffsetRegNum = OffsetRegNum;
Res.Mem.ShiftAmount = ShiftAmount; Op->Mem.OffsetRegShifted = OffsetRegShifted;
Res.Mem.Preindexed = Preindexed; Op->Mem.ShiftType = ShiftType;
Res.Mem.Postindexed = Postindexed; Op->Mem.ShiftAmount = ShiftAmount;
Res.Mem.Negative = Negative; Op->Mem.Preindexed = Preindexed;
Res.Mem.Writeback = Writeback; Op->Mem.Postindexed = Postindexed;
return Res; Op->Mem.Negative = Negative;
Op->Mem.Writeback = Writeback;
Op->StartLoc = S;
Op->EndLoc = E;
} }
}; };
@ -221,7 +267,9 @@ struct ARMOperand : public MCParsedAsmOperand {
/// and false is returned. Else true is returned and no token is eaten. /// and false is returned. Else true is returned and no token is eaten.
/// TODO this is likely to change to allow different register types and or to /// TODO this is likely to change to allow different register types and or to
/// parse for a specific register type. /// parse for a specific register type.
bool ARMAsmParser::MaybeParseRegister(ARMOperand &Op, bool ParseWriteBack) { bool ARMAsmParser::MaybeParseRegister
(OwningPtr<ARMOperand> &Op, bool ParseWriteBack) {
SMLoc S, E;
const AsmToken &Tok = Parser.getTok(); const AsmToken &Tok = Parser.getTok();
assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
@ -232,27 +280,35 @@ bool ARMAsmParser::MaybeParseRegister(ARMOperand &Op, bool ParseWriteBack) {
RegNum = MatchRegisterName(Tok.getString()); RegNum = MatchRegisterName(Tok.getString());
if (RegNum == -1) if (RegNum == -1)
return true; return true;
S = Tok.getLoc();
Parser.Lex(); // Eat identifier token. Parser.Lex(); // Eat identifier token.
E = Parser.getTok().getLoc();
bool Writeback = false; bool Writeback = false;
if (ParseWriteBack) { if (ParseWriteBack) {
const AsmToken &ExclaimTok = Parser.getTok(); const AsmToken &ExclaimTok = Parser.getTok();
if (ExclaimTok.is(AsmToken::Exclaim)) { if (ExclaimTok.is(AsmToken::Exclaim)) {
E = ExclaimTok.getLoc();
Writeback = true; Writeback = true;
Parser.Lex(); // Eat exclaim token Parser.Lex(); // Eat exclaim token
} }
} }
Op = ARMOperand::CreateReg(RegNum, Writeback); ARMOperand::CreateReg(Op, RegNum, Writeback, S, E);
return false; return false;
} }
/// Parse a register list, return false if successful else return true or an /// Parse a register list, return false if successful else return true or an
/// error. The first token must be a '{' when called. /// error. The first token must be a '{' when called.
bool ARMAsmParser::ParseRegisterList(ARMOperand &Op) { bool ARMAsmParser::ParseRegisterList(OwningPtr<ARMOperand> &Op) {
SMLoc S, E;
assert(Parser.getTok().is(AsmToken::LCurly) && assert(Parser.getTok().is(AsmToken::LCurly) &&
"Token is not an Left Curly Brace"); "Token is not an Left Curly Brace");
S = Parser.getTok().getLoc();
Parser.Lex(); // Eat left curly brace token. Parser.Lex(); // Eat left curly brace token.
const AsmToken &RegTok = Parser.getTok(); const AsmToken &RegTok = Parser.getTok();
@ -290,6 +346,7 @@ bool ARMAsmParser::ParseRegisterList(ARMOperand &Op) {
const AsmToken &RCurlyTok = Parser.getTok(); const AsmToken &RCurlyTok = Parser.getTok();
if (RCurlyTok.isNot(AsmToken::RCurly)) if (RCurlyTok.isNot(AsmToken::RCurly))
return Error(RCurlyTok.getLoc(), "'}' expected"); return Error(RCurlyTok.getLoc(), "'}' expected");
E = RCurlyTok.getLoc();
Parser.Lex(); // Eat left curly brace token. Parser.Lex(); // Eat left curly brace token.
return false; return false;
@ -299,9 +356,11 @@ bool ARMAsmParser::ParseRegisterList(ARMOperand &Op) {
/// or an error. The first token must be a '[' when called. /// or an error. The first token must be a '[' when called.
/// TODO Only preindexing and postindexing addressing are started, unindexed /// TODO Only preindexing and postindexing addressing are started, unindexed
/// with option, etc are still to do. /// with option, etc are still to do.
bool ARMAsmParser::ParseMemory(ARMOperand &Op) { bool ARMAsmParser::ParseMemory(OwningPtr<ARMOperand> &Op) {
SMLoc S, E;
assert(Parser.getTok().is(AsmToken::LBrac) && assert(Parser.getTok().is(AsmToken::LBrac) &&
"Token is not an Left Bracket"); "Token is not an Left Bracket");
S = Parser.getTok().getLoc();
Parser.Lex(); // Eat left bracket token. Parser.Lex(); // Eat left bracket token.
const AsmToken &BaseRegTok = Parser.getTok(); const AsmToken &BaseRegTok = Parser.getTok();
@ -309,7 +368,7 @@ bool ARMAsmParser::ParseMemory(ARMOperand &Op) {
return Error(BaseRegTok.getLoc(), "register expected"); return Error(BaseRegTok.getLoc(), "register expected");
if (MaybeParseRegister(Op, false)) if (MaybeParseRegister(Op, false))
return Error(BaseRegTok.getLoc(), "register expected"); return Error(BaseRegTok.getLoc(), "register expected");
int BaseRegNum = Op.getReg(); int BaseRegNum = Op->getReg();
bool Preindexed = false; bool Preindexed = false;
bool Postindexed = false; bool Postindexed = false;
@ -329,21 +388,23 @@ bool ARMAsmParser::ParseMemory(ARMOperand &Op) {
const MCExpr *ShiftAmount; const MCExpr *ShiftAmount;
const MCExpr *Offset; const MCExpr *Offset;
if(ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount, if(ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount,
Offset, OffsetIsReg, OffsetRegNum)) Offset, OffsetIsReg, OffsetRegNum, E))
return true; return true;
const AsmToken &RBracTok = Parser.getTok(); const AsmToken &RBracTok = Parser.getTok();
if (RBracTok.isNot(AsmToken::RBrac)) if (RBracTok.isNot(AsmToken::RBrac))
return Error(RBracTok.getLoc(), "']' expected"); return Error(RBracTok.getLoc(), "']' expected");
E = RBracTok.getLoc();
Parser.Lex(); // Eat right bracket token. Parser.Lex(); // Eat right bracket token.
const AsmToken &ExclaimTok = Parser.getTok(); const AsmToken &ExclaimTok = Parser.getTok();
if (ExclaimTok.is(AsmToken::Exclaim)) { if (ExclaimTok.is(AsmToken::Exclaim)) {
E = ExclaimTok.getLoc();
Writeback = true; Writeback = true;
Parser.Lex(); // Eat exclaim token Parser.Lex(); // Eat exclaim token
} }
Op = ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum, ARMOperand::CreateMem(Op, BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
OffsetRegShifted, ShiftType, ShiftAmount, OffsetRegShifted, ShiftType, ShiftAmount,
Preindexed, Postindexed, Negative, Writeback); Preindexed, Postindexed, Negative, Writeback, S, E);
return false; return false;
} }
// The "[Rn" we have so far was not followed by a comma. // The "[Rn" we have so far was not followed by a comma.
@ -352,6 +413,7 @@ bool ARMAsmParser::ParseMemory(ARMOperand &Op) {
// the "[Rn". // the "[Rn".
Postindexed = true; Postindexed = true;
Writeback = true; Writeback = true;
E = Tok.getLoc();
Parser.Lex(); // Eat right bracket token. Parser.Lex(); // Eat right bracket token.
int OffsetRegNum = 0; int OffsetRegNum = 0;
@ -366,13 +428,14 @@ bool ARMAsmParser::ParseMemory(ARMOperand &Op) {
return Error(NextTok.getLoc(), "',' expected"); return Error(NextTok.getLoc(), "',' expected");
Parser.Lex(); // Eat comma token. Parser.Lex(); // Eat comma token.
if(ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, if(ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType,
ShiftAmount, Offset, OffsetIsReg, OffsetRegNum)) ShiftAmount, Offset, OffsetIsReg, OffsetRegNum,
E))
return true; return true;
} }
Op = ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum, ARMOperand::CreateMem(Op, BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
OffsetRegShifted, ShiftType, ShiftAmount, OffsetRegShifted, ShiftType, ShiftAmount,
Preindexed, Postindexed, Negative, Writeback); Preindexed, Postindexed, Negative, Writeback, S, E);
return false; return false;
} }
@ -387,18 +450,20 @@ bool ARMAsmParser::ParseMemory(ARMOperand &Op) {
/// #offset /// #offset
/// we return false on success or an error otherwise. /// we return false on success or an error otherwise.
bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative, bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
bool &OffsetRegShifted, bool &OffsetRegShifted,
enum ShiftType &ShiftType, enum ShiftType &ShiftType,
const MCExpr *&ShiftAmount, const MCExpr *&ShiftAmount,
const MCExpr *&Offset, const MCExpr *&Offset,
bool &OffsetIsReg, bool &OffsetIsReg,
int &OffsetRegNum) { int &OffsetRegNum,
ARMOperand Op; SMLoc &E) {
OwningPtr<ARMOperand> Op;
Negative = false; Negative = false;
OffsetRegShifted = false; OffsetRegShifted = false;
OffsetIsReg = false; OffsetIsReg = false;
OffsetRegNum = -1; OffsetRegNum = -1;
const AsmToken &NextTok = Parser.getTok(); const AsmToken &NextTok = Parser.getTok();
E = NextTok.getLoc();
if (NextTok.is(AsmToken::Plus)) if (NextTok.is(AsmToken::Plus))
Parser.Lex(); // Eat plus token. Parser.Lex(); // Eat plus token.
else if (NextTok.is(AsmToken::Minus)) { else if (NextTok.is(AsmToken::Minus)) {
@ -409,8 +474,10 @@ bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
const AsmToken &OffsetRegTok = Parser.getTok(); const AsmToken &OffsetRegTok = Parser.getTok();
if (OffsetRegTok.is(AsmToken::Identifier)) { if (OffsetRegTok.is(AsmToken::Identifier)) {
OffsetIsReg = !MaybeParseRegister(Op, false); OffsetIsReg = !MaybeParseRegister(Op, false);
if (OffsetIsReg) if (OffsetIsReg) {
OffsetRegNum = Op.getReg(); E = Op->getEndLoc();
OffsetRegNum = Op->getReg();
}
} }
// If we parsed a register as the offset then their can be a shift after that // If we parsed a register as the offset then their can be a shift after that
if (OffsetRegNum != -1) { if (OffsetRegNum != -1) {
@ -420,7 +487,7 @@ bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
Parser.Lex(); // Eat comma token. Parser.Lex(); // Eat comma token.
const AsmToken &Tok = Parser.getTok(); const AsmToken &Tok = Parser.getTok();
if (ParseShift(ShiftType, ShiftAmount)) if (ParseShift(ShiftType, ShiftAmount, E))
return Error(Tok.getLoc(), "shift expected"); return Error(Tok.getLoc(), "shift expected");
OffsetRegShifted = true; OffsetRegShifted = true;
} }
@ -430,10 +497,12 @@ bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
const AsmToken &HashTok = Parser.getTok(); const AsmToken &HashTok = Parser.getTok();
if (HashTok.isNot(AsmToken::Hash)) if (HashTok.isNot(AsmToken::Hash))
return Error(HashTok.getLoc(), "'#' expected"); return Error(HashTok.getLoc(), "'#' expected");
Parser.Lex(); // Eat hash token. Parser.Lex(); // Eat hash token.
if (getParser().ParseExpression(Offset)) if (getParser().ParseExpression(Offset))
return true; return true;
E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
} }
return false; return false;
} }
@ -442,7 +511,9 @@ bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
/// ( lsl | lsr | asr | ror ) , # shift_amount /// ( lsl | lsr | asr | ror ) , # shift_amount
/// rrx /// rrx
/// and returns true if it parses a shift otherwise it returns false. /// and returns true if it parses a shift otherwise it returns false.
bool ARMAsmParser::ParseShift(ShiftType &St, const MCExpr *&ShiftAmount) { bool ARMAsmParser::ParseShift(ShiftType &St,
const MCExpr *&ShiftAmount,
SMLoc &E) {
const AsmToken &Tok = Parser.getTok(); const AsmToken &Tok = Parser.getTok();
if (Tok.isNot(AsmToken::Identifier)) if (Tok.isNot(AsmToken::Identifier))
return true; return true;
@ -550,7 +621,9 @@ MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
/// Parse a arm instruction operand. For now this parses the operand regardless /// Parse a arm instruction operand. For now this parses the operand regardless
/// of the mnemonic. /// of the mnemonic.
bool ARMAsmParser::ParseOperand(ARMOperand &Op) { bool ARMAsmParser::ParseOperand(OwningPtr<ARMOperand> &Op) {
SMLoc S, E;
switch (getLexer().getKind()) { switch (getLexer().getKind()) {
case AsmToken::Identifier: case AsmToken::Identifier:
if (!MaybeParseRegister(Op, true)) if (!MaybeParseRegister(Op, true))
@ -558,9 +631,11 @@ bool ARMAsmParser::ParseOperand(ARMOperand &Op) {
// This was not a register so parse other operands that start with an // This was not a register so parse other operands that start with an
// identifier (like labels) as expressions and create them as immediates. // identifier (like labels) as expressions and create them as immediates.
const MCExpr *IdVal; const MCExpr *IdVal;
S = Parser.getTok().getLoc();
if (getParser().ParseExpression(IdVal)) if (getParser().ParseExpression(IdVal))
return true; return true;
Op = ARMOperand::CreateImm(IdVal); E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
ARMOperand::CreateImm(Op, IdVal, S, E);
return false; return false;
case AsmToken::LBrac: case AsmToken::LBrac:
return ParseMemory(Op); return ParseMemory(Op);
@ -569,11 +644,13 @@ bool ARMAsmParser::ParseOperand(ARMOperand &Op) {
case AsmToken::Hash: case AsmToken::Hash:
// #42 -> immediate. // #42 -> immediate.
// TODO: ":lower16:" and ":upper16:" modifiers after # before immediate // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
S = Parser.getTok().getLoc();
Parser.Lex(); Parser.Lex();
const MCExpr *ImmVal; const MCExpr *ImmVal;
if (getParser().ParseExpression(ImmVal)) if (getParser().ParseExpression(ImmVal))
return true; return true;
Op = ARMOperand::CreateImm(ImmVal); E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
ARMOperand::CreateImm(Op, ImmVal, S, E);
return false; return false;
default: default:
return Error(Parser.getTok().getLoc(), "unexpected token in operand"); return Error(Parser.getTok().getLoc(), "unexpected token in operand");
@ -583,22 +660,25 @@ bool ARMAsmParser::ParseOperand(ARMOperand &Op) {
/// Parse an arm instruction mnemonic followed by its operands. /// Parse an arm instruction mnemonic followed by its operands.
bool ARMAsmParser::ParseInstruction(const StringRef &Name, SMLoc NameLoc, bool ARMAsmParser::ParseInstruction(const StringRef &Name, SMLoc NameLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands) { SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Operands.push_back(new ARMOperand(ARMOperand::CreateToken(Name))); OwningPtr<ARMOperand> Op;
ARMOperand::CreateToken(Op, Name, NameLoc);
Operands.push_back(Op.take());
SMLoc Loc = Parser.getTok().getLoc(); SMLoc Loc = Parser.getTok().getLoc();
if (getLexer().isNot(AsmToken::EndOfStatement)) { if (getLexer().isNot(AsmToken::EndOfStatement)) {
// Read the first operand. // Read the first operand.
ARMOperand Op; OwningPtr<ARMOperand> Op;
if (ParseOperand(Op)) return true; if (ParseOperand(Op)) return true;
Operands.push_back(new ARMOperand(Op)); Operands.push_back(Op.take());
while (getLexer().is(AsmToken::Comma)) { while (getLexer().is(AsmToken::Comma)) {
Parser.Lex(); // Eat the comma. Parser.Lex(); // Eat the comma.
// Parse and remember the operand. // Parse and remember the operand.
if (ParseOperand(Op)) return true; if (ParseOperand(Op)) return true;
Operands.push_back(new ARMOperand(Op)); Operands.push_back(Op.take());
} }
} }
return false; return false;