forked from OSchip/llvm-project
[AArch64][SVE] Asm: Support for saturating INC/DEC (32bit scalar) instructions.
The variants added by this patch are: - SQINC signed increment, e.g. sqinc x0, w0, all, mul #4 - SQDEC signed decrement, e.g. sqdec x0, w0, all, mul #4 - UQINC unsigned increment, e.g. uqinc w0, all, mul #4 - UQDEC unsigned decrement, e.g. uqdec w0, all, mul #4 This patch includes asmparser changes to parse a GPR64 as a GPR32 in order to satisfy the constraint check: x0 == GPR64(w0) in: sqinc x0, w0, all, mul #4 ^___^ (must match) Reviewers: rengolin, fhahn, SjoerdMeijer, samparker, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D47716 llvm-svn: 334980
This commit is contained in:
Sander de Smalen
parent
78c62966c2
commit
7ac9e193ec
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@ -179,11 +179,23 @@ def CondCode : AsmOperandClass {
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// A 32-bit register pasrsed as 64-bit
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def GPR32as64Operand : AsmOperandClass {
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let Name = "GPR32as64";
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let ParserMethod =
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"tryParseGPROperand<false, RegConstraintEqualityTy::EqualsSubReg>";
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}
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def GPR32as64 : RegisterOperand<GPR32> {
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let ParserMatchClass = GPR32as64Operand;
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}
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// A 64-bit register pasrsed as 32-bit
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def GPR64as32Operand : AsmOperandClass {
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let Name = "GPR64as32";
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let ParserMethod =
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"tryParseGPROperand<false, RegConstraintEqualityTy::EqualsSuperReg>";
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}
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def GPR64as32 : RegisterOperand<GPR64, "printGPR64as32"> {
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let ParserMatchClass = GPR64as32Operand;
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}
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// 8-bit immediate for AdvSIMD where 64-bit values of the form:
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// aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh
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// are encoded as the eight bit value 'abcdefgh'.
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@ -527,21 +527,37 @@ let Predicates = [HasSVE] in {
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defm CMPLO_WIDE_PPzZZ : sve_int_cmp_1_wide<0b110, "cmplo">;
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defm CMPLS_WIDE_PPzZZ : sve_int_cmp_1_wide<0b111, "cmpls">;
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defm SQINCB_XPiWdI : sve_int_pred_pattern_b_s32<0b00000, "sqincb">;
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defm UQINCB_WPiI : sve_int_pred_pattern_b_u32<0b00001, "uqincb">;
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defm SQDECB_XPiWdI : sve_int_pred_pattern_b_s32<0b00010, "sqdecb">;
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defm UQDECB_WPiI : sve_int_pred_pattern_b_u32<0b00011, "uqdecb">;
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defm SQINCB_XPiI : sve_int_pred_pattern_b_x64<0b00100, "sqincb">;
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defm UQINCB_XPiI : sve_int_pred_pattern_b_x64<0b00101, "uqincb">;
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defm SQDECB_XPiI : sve_int_pred_pattern_b_x64<0b00110, "sqdecb">;
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defm UQDECB_XPiI : sve_int_pred_pattern_b_x64<0b00111, "uqdecb">;
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defm SQINCH_XPiWdI : sve_int_pred_pattern_b_s32<0b01000, "sqinch">;
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defm UQINCH_WPiI : sve_int_pred_pattern_b_u32<0b01001, "uqinch">;
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defm SQDECH_XPiWdI : sve_int_pred_pattern_b_s32<0b01010, "sqdech">;
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defm UQDECH_WPiI : sve_int_pred_pattern_b_u32<0b01011, "uqdech">;
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defm SQINCH_XPiI : sve_int_pred_pattern_b_x64<0b01100, "sqinch">;
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defm UQINCH_XPiI : sve_int_pred_pattern_b_x64<0b01101, "uqinch">;
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defm SQDECH_XPiI : sve_int_pred_pattern_b_x64<0b01110, "sqdech">;
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defm UQDECH_XPiI : sve_int_pred_pattern_b_x64<0b01111, "uqdech">;
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defm SQINCW_XPiWdI : sve_int_pred_pattern_b_s32<0b10000, "sqincw">;
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defm UQINCW_WPiI : sve_int_pred_pattern_b_u32<0b10001, "uqincw">;
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defm SQDECW_XPiWdI : sve_int_pred_pattern_b_s32<0b10010, "sqdecw">;
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defm UQDECW_WPiI : sve_int_pred_pattern_b_u32<0b10011, "uqdecw">;
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defm SQINCW_XPiI : sve_int_pred_pattern_b_x64<0b10100, "sqincw">;
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defm UQINCW_XPiI : sve_int_pred_pattern_b_x64<0b10101, "uqincw">;
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defm SQDECW_XPiI : sve_int_pred_pattern_b_x64<0b10110, "sqdecw">;
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defm UQDECW_XPiI : sve_int_pred_pattern_b_x64<0b10111, "uqdecw">;
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defm SQINCD_XPiWdI : sve_int_pred_pattern_b_s32<0b11000, "sqincd">;
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defm UQINCD_WPiI : sve_int_pred_pattern_b_u32<0b11001, "uqincd">;
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defm SQDECD_XPiWdI : sve_int_pred_pattern_b_s32<0b11010, "sqdecd">;
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defm UQDECD_WPiI : sve_int_pred_pattern_b_u32<0b11011, "uqdecd">;
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defm SQINCD_XPiI : sve_int_pred_pattern_b_x64<0b11100, "sqincd">;
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defm UQINCD_XPiI : sve_int_pred_pattern_b_x64<0b11101, "uqincd">;
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defm SQDECD_XPiI : sve_int_pred_pattern_b_x64<0b11110, "sqdecd">;
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@ -66,6 +66,12 @@ enum class RegKind {
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SVEPredicateVector
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};
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enum RegConstraintEqualityTy {
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EqualsReg,
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EqualsSuperReg,
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EqualsSubReg
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};
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class AArch64AsmParser : public MCTargetAsmParser {
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private:
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StringRef Mnemonic; ///< Instruction mnemonic.
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@ -92,7 +98,8 @@ private:
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bool parseOperand(OperandVector &Operands, bool isCondCode,
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bool invertCondCode);
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bool showMatchError(SMLoc Loc, unsigned ErrCode, OperandVector &Operands);
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bool showMatchError(SMLoc Loc, unsigned ErrCode, uint64_t ErrorInfo,
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OperandVector &Operands);
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bool parseDirectiveArch(SMLoc L);
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bool parseDirectiveCPU(SMLoc L);
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@ -139,7 +146,8 @@ private:
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bool tryParseNeonVectorRegister(OperandVector &Operands);
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OperandMatchResultTy tryParseVectorIndex(OperandVector &Operands);
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OperandMatchResultTy tryParseGPRSeqPair(OperandVector &Operands);
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template <bool ParseShiftExtend>
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template <bool ParseShiftExtend,
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RegConstraintEqualityTy EqTy = RegConstraintEqualityTy::EqualsReg>
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OperandMatchResultTy tryParseGPROperand(OperandVector &Operands);
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template <bool ParseShiftExtend, bool ParseSuffix>
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OperandMatchResultTy tryParseSVEDataVector(OperandVector &Operands);
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@ -177,6 +185,8 @@ public:
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setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
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}
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bool regsEqual(const MCParsedAsmOperand &Op1,
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const MCParsedAsmOperand &Op2) const override;
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bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
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SMLoc NameLoc, OperandVector &Operands) override;
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bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
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@ -231,6 +241,10 @@ private:
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RegKind Kind;
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int ElementWidth;
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// The register may be allowed as a different register class,
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// e.g. for GPR64as32 or GPR32as64.
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RegConstraintEqualityTy EqualityTy;
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// In some cases the shift/extend needs to be explicitly parsed together
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// with the register, rather than as a separate operand. This is needed
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// for addressing modes where the instruction as a whole dictates the
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@ -446,6 +460,11 @@ public:
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return Reg.RegNum;
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}
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RegConstraintEqualityTy getRegEqualityTy() const {
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assert(Kind == k_Register && "Invalid access!");
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return Reg.EqualityTy;
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}
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unsigned getVectorListStart() const {
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assert(Kind == k_VectorList && "Invalid access!");
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return VectorList.RegNum;
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@ -1002,6 +1021,11 @@ public:
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AArch64MCRegisterClasses[AArch64::GPR64RegClassID].contains(Reg.RegNum);
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}
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bool isGPR64as32() const {
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return Kind == k_Register && Reg.Kind == RegKind::Scalar &&
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AArch64MCRegisterClasses[AArch64::GPR32RegClassID].contains(Reg.RegNum);
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}
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bool isWSeqPair() const {
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return Kind == k_Register && Reg.Kind == RegKind::Scalar &&
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AArch64MCRegisterClasses[AArch64::WSeqPairsClassRegClassID].contains(
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@ -1318,6 +1342,18 @@ public:
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Inst.addOperand(MCOperand::createReg(Reg));
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}
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void addGPR64as32Operands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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assert(
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AArch64MCRegisterClasses[AArch64::GPR32RegClassID].contains(getReg()));
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const MCRegisterInfo *RI = Ctx.getRegisterInfo();
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uint32_t Reg = RI->getRegClass(AArch64::GPR64RegClassID).getRegister(
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RI->getEncodingValue(getReg()));
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Inst.addOperand(MCOperand::createReg(Reg));
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}
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template <int Width>
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void addFPRasZPRRegOperands(MCInst &Inst, unsigned N) const {
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unsigned Base;
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@ -1668,6 +1704,7 @@ public:
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static std::unique_ptr<AArch64Operand>
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CreateReg(unsigned RegNum, RegKind Kind, SMLoc S, SMLoc E, MCContext &Ctx,
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RegConstraintEqualityTy EqTy = RegConstraintEqualityTy::EqualsReg,
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AArch64_AM::ShiftExtendType ExtTy = AArch64_AM::LSL,
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unsigned ShiftAmount = 0,
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unsigned HasExplicitAmount = false) {
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@ -1675,6 +1712,7 @@ public:
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Op->Reg.RegNum = RegNum;
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Op->Reg.Kind = Kind;
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Op->Reg.ElementWidth = 0;
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Op->Reg.EqualityTy = EqTy;
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Op->Reg.ShiftExtend.Type = ExtTy;
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Op->Reg.ShiftExtend.Amount = ShiftAmount;
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Op->Reg.ShiftExtend.HasExplicitAmount = HasExplicitAmount;
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@ -1692,7 +1730,7 @@ public:
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assert((Kind == RegKind::NeonVector || Kind == RegKind::SVEDataVector ||
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Kind == RegKind::SVEPredicateVector) &&
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"Invalid vector kind");
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auto Op = CreateReg(RegNum, Kind, S, E, Ctx, ExtTy, ShiftAmount,
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auto Op = CreateReg(RegNum, Kind, S, E, Ctx, EqualsReg, ExtTy, ShiftAmount,
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HasExplicitAmount);
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Op->Reg.ElementWidth = ElementWidth;
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return Op;
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@ -3164,7 +3202,7 @@ AArch64AsmParser::tryParseGPR64sp0Operand(OperandVector &Operands) {
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return MatchOperand_Success;
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}
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template <bool ParseShiftExtend>
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template <bool ParseShiftExtend, RegConstraintEqualityTy EqTy>
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OperandMatchResultTy
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AArch64AsmParser::tryParseGPROperand(OperandVector &Operands) {
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SMLoc StartLoc = getLoc();
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@ -3177,7 +3215,7 @@ AArch64AsmParser::tryParseGPROperand(OperandVector &Operands) {
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// No shift/extend is the default.
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if (!ParseShiftExtend || getParser().getTok().isNot(AsmToken::Comma)) {
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Operands.push_back(AArch64Operand::CreateReg(
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RegNum, RegKind::Scalar, StartLoc, getLoc(), getContext()));
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RegNum, RegKind::Scalar, StartLoc, getLoc(), getContext(), EqTy));
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return MatchOperand_Success;
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}
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@ -3191,10 +3229,10 @@ AArch64AsmParser::tryParseGPROperand(OperandVector &Operands) {
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return Res;
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auto Ext = static_cast<AArch64Operand*>(ExtOpnd.back().get());
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Operands.push_back(AArch64Operand::CreateReg(RegNum, RegKind::Scalar,
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StartLoc, Ext->getEndLoc(), getContext(),
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Ext->getShiftExtendType(), Ext->getShiftExtendAmount(),
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Ext->hasShiftExtendAmount()));
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Operands.push_back(AArch64Operand::CreateReg(
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RegNum, RegKind::Scalar, StartLoc, Ext->getEndLoc(), getContext(), EqTy,
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Ext->getShiftExtendType(), Ext->getShiftExtendAmount(),
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Ext->hasShiftExtendAmount()));
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return MatchOperand_Success;
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}
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@ -3412,6 +3450,30 @@ bool AArch64AsmParser::parseOperand(OperandVector &Operands, bool isCondCode,
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}
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}
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bool AArch64AsmParser::regsEqual(const MCParsedAsmOperand &Op1,
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const MCParsedAsmOperand &Op2) const {
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auto &AOp1 = static_cast<const AArch64Operand&>(Op1);
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auto &AOp2 = static_cast<const AArch64Operand&>(Op2);
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if (AOp1.getRegEqualityTy() == RegConstraintEqualityTy::EqualsReg &&
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AOp2.getRegEqualityTy() == RegConstraintEqualityTy::EqualsReg)
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return MCTargetAsmParser::regsEqual(Op1, Op2);
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assert(AOp1.isScalarReg() && AOp2.isScalarReg() &&
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"Testing equality of non-scalar registers not supported");
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// Check if a registers match their sub/super register classes.
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if (AOp1.getRegEqualityTy() == EqualsSuperReg)
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return getXRegFromWReg(Op1.getReg()) == Op2.getReg();
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if (AOp1.getRegEqualityTy() == EqualsSubReg)
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return getWRegFromXReg(Op1.getReg()) == Op2.getReg();
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if (AOp2.getRegEqualityTy() == EqualsSuperReg)
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return getXRegFromWReg(Op2.getReg()) == Op1.getReg();
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if (AOp2.getRegEqualityTy() == EqualsSubReg)
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return getWRegFromXReg(Op2.getReg()) == Op1.getReg();
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return false;
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}
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/// ParseInstruction - Parse an AArch64 instruction mnemonic followed by its
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/// operands.
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bool AArch64AsmParser::ParseInstruction(ParseInstructionInfo &Info,
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@ -3765,10 +3827,22 @@ static std::string AArch64MnemonicSpellCheck(StringRef S, uint64_t FBS,
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unsigned VariantID = 0);
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bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
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uint64_t ErrorInfo,
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OperandVector &Operands) {
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switch (ErrCode) {
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case Match_InvalidTiedOperand:
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return Error(Loc, "operand must match destination register");
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case Match_InvalidTiedOperand: {
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RegConstraintEqualityTy EqTy =
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static_cast<const AArch64Operand &>(*Operands[ErrorInfo])
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.getRegEqualityTy();
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switch (EqTy) {
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case RegConstraintEqualityTy::EqualsSubReg:
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return Error(Loc, "operand must be 64-bit form of destination register");
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case RegConstraintEqualityTy::EqualsSuperReg:
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return Error(Loc, "operand must be 32-bit form of destination register");
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case RegConstraintEqualityTy::EqualsReg:
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return Error(Loc, "operand must match destination register");
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}
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}
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case Match_MissingFeature:
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return Error(Loc,
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"instruction requires a CPU feature not currently enabled");
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@ -4389,7 +4463,7 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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return Error(IDLoc, Msg);
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}
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case Match_MnemonicFail:
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return showMatchError(IDLoc, MatchResult, Operands);
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return showMatchError(IDLoc, MatchResult, ErrorInfo, Operands);
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case Match_InvalidOperand: {
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SMLoc ErrorLoc = IDLoc;
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@ -4408,7 +4482,7 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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((AArch64Operand &)*Operands[ErrorInfo]).isTokenSuffix())
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MatchResult = Match_InvalidSuffix;
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return showMatchError(ErrorLoc, MatchResult, Operands);
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return showMatchError(ErrorLoc, MatchResult, ErrorInfo, Operands);
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}
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case Match_InvalidTiedOperand:
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case Match_InvalidMemoryIndexed1:
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@ -4546,7 +4620,7 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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SMLoc ErrorLoc = ((AArch64Operand &)*Operands[ErrorInfo]).getStartLoc();
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if (ErrorLoc == SMLoc())
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ErrorLoc = IDLoc;
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return showMatchError(ErrorLoc, MatchResult, Operands);
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return showMatchError(ErrorLoc, MatchResult, ErrorInfo, Operands);
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}
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}
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@ -1527,3 +1527,10 @@ void AArch64InstPrinter::printExactFPImm(const MCInst *MI, unsigned OpNum,
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unsigned Val = MI->getOperand(OpNum).getImm();
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O << "#" << (Val ? Imm1Desc->Repr : Imm0Desc->Repr);
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}
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void AArch64InstPrinter::printGPR64as32(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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unsigned Reg = MI->getOperand(OpNum).getReg();
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O << getRegisterName(getWRegFromXReg(Reg));
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}
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@ -180,6 +180,8 @@ protected:
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template <char = 0>
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void printSVERegOp(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printGPR64as32(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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template <int Width>
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void printZPRasFPR(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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@ -333,9 +333,32 @@ class sve_int_pred_pattern_b<bits<5> opc, string asm, RegisterOperand dt,
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let Inst{9-5} = pattern;
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let Inst{4-0} = Rdn;
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// Signed 32bit forms require their GPR operand printed.
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let AsmString = !if(!eq(opc{2,0}, 0b00),
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!strconcat(asm, "\t$Rdn, $_Rdn, $pattern, mul $imm4"),
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!strconcat(asm, "\t$Rdn, $pattern, mul $imm4"));
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let Constraints = "$Rdn = $_Rdn";
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}
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multiclass sve_int_pred_pattern_b_s32<bits<5> opc, string asm> {
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def NAME : sve_int_pred_pattern_b<opc, asm, GPR64z, GPR64as32>;
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def : InstAlias<asm # "\t$Rd, $Rn, $pattern",
|
||||
(!cast<Instruction>(NAME) GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1), 1>;
|
||||
def : InstAlias<asm # "\t$Rd, $Rn",
|
||||
(!cast<Instruction>(NAME) GPR64z:$Rd, GPR64as32:$Rn, 0b11111, 1), 2>;
|
||||
}
|
||||
|
||||
multiclass sve_int_pred_pattern_b_u32<bits<5> opc, string asm> {
|
||||
def NAME : sve_int_pred_pattern_b<opc, asm, GPR32z, GPR32z>;
|
||||
|
||||
def : InstAlias<asm # "\t$Rdn, $pattern",
|
||||
(!cast<Instruction>(NAME) GPR32z:$Rdn, sve_pred_enum:$pattern, 1), 1>;
|
||||
def : InstAlias<asm # "\t$Rdn",
|
||||
(!cast<Instruction>(NAME) GPR32z:$Rdn, 0b11111, 1), 2>;
|
||||
}
|
||||
|
||||
multiclass sve_int_pred_pattern_b_x64<bits<5> opc, string asm> {
|
||||
def NAME : sve_int_pred_pattern_b<opc, asm, GPR64z, GPR64z>;
|
||||
|
||||
|
|
|
|||
|
|
@ -19,6 +19,20 @@ sqdecb sp
|
|||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Operands not matching up
|
||||
|
||||
sqdecb x0, w1
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register
|
||||
// CHECK-NEXT: sqdecb x0, w1
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
sqdecb x0, x1
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
|
||||
// CHECK-NEXT: sqdecb x0, x1
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Immediate not compatible with encode/decode function.
|
||||
|
||||
|
|
|
|||
|
|
@ -36,6 +36,47 @@ sqdecb x0, all, mul #16
|
|||
// CHECK-UNKNOWN: e0 fb 3f 04 <unknown>
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------//
|
||||
// Test 32-bit form (x0, w0) and its aliases
|
||||
// ---------------------------------------------------------------------------//
|
||||
|
||||
sqdecb x0, w0
|
||||
// CHECK-INST: sqdecb x0, w0
|
||||
// CHECK-ENCODING: [0xe0,0xfb,0x20,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 fb 20 04 <unknown>
|
||||
|
||||
sqdecb x0, w0, all
|
||||
// CHECK-INST: sqdecb x0, w0
|
||||
// CHECK-ENCODING: [0xe0,0xfb,0x20,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 fb 20 04 <unknown>
|
||||
|
||||
sqdecb x0, w0, all, mul #1
|
||||
// CHECK-INST: sqdecb x0, w0
|
||||
// CHECK-ENCODING: [0xe0,0xfb,0x20,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 fb 20 04 <unknown>
|
||||
|
||||
sqdecb x0, w0, all, mul #16
|
||||
// CHECK-INST: sqdecb x0, w0, all, mul #16
|
||||
// CHECK-ENCODING: [0xe0,0xfb,0x2f,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 fb 2f 04 <unknown>
|
||||
|
||||
sqdecb x0, w0, pow2
|
||||
// CHECK-INST: sqdecb x0, w0, pow2
|
||||
// CHECK-ENCODING: [0x00,0xf8,0x20,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 f8 20 04 <unknown>
|
||||
|
||||
sqdecb x0, w0, pow2, mul #16
|
||||
// CHECK-INST: sqdecb x0, w0, pow2, mul #16
|
||||
// CHECK-ENCODING: [0x00,0xf8,0x2f,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 f8 2f 04 <unknown>
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------//
|
||||
// Test all patterns for 64-bit form
|
||||
// ---------------------------------------------------------------------------//
|
||||
|
|
|
|||
|
|
@ -19,6 +19,20 @@ sqdecd sp
|
|||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Operands not matching up
|
||||
|
||||
sqdecd x0, w1
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register
|
||||
// CHECK-NEXT: sqdecd x0, w1
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
sqdecd x0, x1
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
|
||||
// CHECK-NEXT: sqdecd x0, x1
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Immediate not compatible with encode/decode function.
|
||||
|
||||
|
|
|
|||
|
|
@ -36,6 +36,47 @@ sqdecd x0, all, mul #16
|
|||
// CHECK-UNKNOWN: e0 fb ff 04 <unknown>
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------//
|
||||
// Test 32-bit form (x0, w0) and its aliases
|
||||
// ---------------------------------------------------------------------------//
|
||||
|
||||
sqdecd x0, w0
|
||||
// CHECK-INST: sqdecd x0, w0
|
||||
// CHECK-ENCODING: [0xe0,0xfb,0xe0,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 fb e0 04 <unknown>
|
||||
|
||||
sqdecd x0, w0, all
|
||||
// CHECK-INST: sqdecd x0, w0
|
||||
// CHECK-ENCODING: [0xe0,0xfb,0xe0,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 fb e0 04 <unknown>
|
||||
|
||||
sqdecd x0, w0, all, mul #1
|
||||
// CHECK-INST: sqdecd x0, w0
|
||||
// CHECK-ENCODING: [0xe0,0xfb,0xe0,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 fb e0 04 <unknown>
|
||||
|
||||
sqdecd x0, w0, all, mul #16
|
||||
// CHECK-INST: sqdecd x0, w0, all, mul #16
|
||||
// CHECK-ENCODING: [0xe0,0xfb,0xef,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 fb ef 04 <unknown>
|
||||
|
||||
sqdecd x0, w0, pow2
|
||||
// CHECK-INST: sqdecd x0, w0, pow2
|
||||
// CHECK-ENCODING: [0x00,0xf8,0xe0,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 f8 e0 04 <unknown>
|
||||
|
||||
sqdecd x0, w0, pow2, mul #16
|
||||
// CHECK-INST: sqdecd x0, w0, pow2, mul #16
|
||||
// CHECK-ENCODING: [0x00,0xf8,0xef,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 f8 ef 04 <unknown>
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------//
|
||||
// Test all patterns for 64-bit form
|
||||
// ---------------------------------------------------------------------------//
|
||||
|
|
|
|||
|
|
@ -19,6 +19,20 @@ sqdech sp
|
|||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Operands not matching up
|
||||
|
||||
sqdech x0, w1
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register
|
||||
// CHECK-NEXT: sqdech x0, w1
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
sqdech x0, x1
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
|
||||
// CHECK-NEXT: sqdech x0, x1
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Immediate not compatible with encode/decode function.
|
||||
|
||||
|
|
|
|||
|
|
@ -36,6 +36,47 @@ sqdech x0, all, mul #16
|
|||
// CHECK-UNKNOWN: e0 fb 7f 04 <unknown>
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------//
|
||||
// Test 32-bit form (x0, w0) and its aliases
|
||||
// ---------------------------------------------------------------------------//
|
||||
|
||||
sqdech x0, w0
|
||||
// CHECK-INST: sqdech x0, w0
|
||||
// CHECK-ENCODING: [0xe0,0xfb,0x60,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 fb 60 04 <unknown>
|
||||
|
||||
sqdech x0, w0, all
|
||||
// CHECK-INST: sqdech x0, w0
|
||||
// CHECK-ENCODING: [0xe0,0xfb,0x60,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 fb 60 04 <unknown>
|
||||
|
||||
sqdech x0, w0, all, mul #1
|
||||
// CHECK-INST: sqdech x0, w0
|
||||
// CHECK-ENCODING: [0xe0,0xfb,0x60,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 fb 60 04 <unknown>
|
||||
|
||||
sqdech x0, w0, all, mul #16
|
||||
// CHECK-INST: sqdech x0, w0, all, mul #16
|
||||
// CHECK-ENCODING: [0xe0,0xfb,0x6f,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 fb 6f 04 <unknown>
|
||||
|
||||
sqdech x0, w0, pow2
|
||||
// CHECK-INST: sqdech x0, w0, pow2
|
||||
// CHECK-ENCODING: [0x00,0xf8,0x60,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 f8 60 04 <unknown>
|
||||
|
||||
sqdech x0, w0, pow2, mul #16
|
||||
// CHECK-INST: sqdech x0, w0, pow2, mul #16
|
||||
// CHECK-ENCODING: [0x00,0xf8,0x6f,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 f8 6f 04 <unknown>
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------//
|
||||
// Test all patterns for 64-bit form
|
||||
// ---------------------------------------------------------------------------//
|
||||
|
|
|
|||
|
|
@ -19,6 +19,20 @@ sqdecw sp
|
|||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Operands not matching up
|
||||
|
||||
sqdecw x0, w1
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register
|
||||
// CHECK-NEXT: sqdecw x0, w1
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
sqdecw x0, x1
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
|
||||
// CHECK-NEXT: sqdecw x0, x1
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Immediate not compatible with encode/decode function.
|
||||
|
||||
|
|
|
|||
|
|
@ -36,6 +36,47 @@ sqdecw x0, all, mul #16
|
|||
// CHECK-UNKNOWN: e0 fb bf 04 <unknown>
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------//
|
||||
// Test 32-bit form (x0, w0) and its aliases
|
||||
// ---------------------------------------------------------------------------//
|
||||
|
||||
sqdecw x0, w0
|
||||
// CHECK-INST: sqdecw x0, w0
|
||||
// CHECK-ENCODING: [0xe0,0xfb,0xa0,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 fb a0 04 <unknown>
|
||||
|
||||
sqdecw x0, w0, all
|
||||
// CHECK-INST: sqdecw x0, w0
|
||||
// CHECK-ENCODING: [0xe0,0xfb,0xa0,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 fb a0 04 <unknown>
|
||||
|
||||
sqdecw x0, w0, all, mul #1
|
||||
// CHECK-INST: sqdecw x0, w0
|
||||
// CHECK-ENCODING: [0xe0,0xfb,0xa0,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 fb a0 04 <unknown>
|
||||
|
||||
sqdecw x0, w0, all, mul #16
|
||||
// CHECK-INST: sqdecw x0, w0, all, mul #16
|
||||
// CHECK-ENCODING: [0xe0,0xfb,0xaf,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 fb af 04 <unknown>
|
||||
|
||||
sqdecw x0, w0, pow2
|
||||
// CHECK-INST: sqdecw x0, w0, pow2
|
||||
// CHECK-ENCODING: [0x00,0xf8,0xa0,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 f8 a0 04 <unknown>
|
||||
|
||||
sqdecw x0, w0, pow2, mul #16
|
||||
// CHECK-INST: sqdecw x0, w0, pow2, mul #16
|
||||
// CHECK-ENCODING: [0x00,0xf8,0xaf,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 f8 af 04 <unknown>
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------//
|
||||
// Test all patterns for 64-bit form
|
||||
// ---------------------------------------------------------------------------//
|
||||
|
|
|
|||
|
|
@ -19,6 +19,20 @@ sqincb sp
|
|||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Operands not matching up
|
||||
|
||||
sqincb x0, w1
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register
|
||||
// CHECK-NEXT: sqincb x0, w1
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
sqincb x0, x0
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
|
||||
// CHECK-NEXT: sqincb x0, x0
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Immediate not compatible with encode/decode function.
|
||||
|
||||
|
|
|
|||
|
|
@ -36,6 +36,47 @@ sqincb x0, all, mul #16
|
|||
// CHECK-UNKNOWN: e0 f3 3f 04 <unknown>
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------//
|
||||
// Test 32-bit form (x0, w0) and its aliases
|
||||
// ---------------------------------------------------------------------------//
|
||||
|
||||
sqincb x0, w0
|
||||
// CHECK-INST: sqincb x0, w0
|
||||
// CHECK-ENCODING: [0xe0,0xf3,0x20,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 f3 20 04 <unknown>
|
||||
|
||||
sqincb x0, w0, all
|
||||
// CHECK-INST: sqincb x0, w0
|
||||
// CHECK-ENCODING: [0xe0,0xf3,0x20,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 f3 20 04 <unknown>
|
||||
|
||||
sqincb x0, w0, all, mul #1
|
||||
// CHECK-INST: sqincb x0, w0
|
||||
// CHECK-ENCODING: [0xe0,0xf3,0x20,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 f3 20 04 <unknown>
|
||||
|
||||
sqincb x0, w0, all, mul #16
|
||||
// CHECK-INST: sqincb x0, w0, all, mul #16
|
||||
// CHECK-ENCODING: [0xe0,0xf3,0x2f,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 f3 2f 04 <unknown>
|
||||
|
||||
sqincb x0, w0, pow2
|
||||
// CHECK-INST: sqincb x0, w0, pow2
|
||||
// CHECK-ENCODING: [0x00,0xf0,0x20,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 f0 20 04 <unknown>
|
||||
|
||||
sqincb x0, w0, pow2, mul #16
|
||||
// CHECK-INST: sqincb x0, w0, pow2, mul #16
|
||||
// CHECK-ENCODING: [0x00,0xf0,0x2f,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 f0 2f 04 <unknown>
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------//
|
||||
// Test all patterns for 64-bit form
|
||||
// ---------------------------------------------------------------------------//
|
||||
|
|
|
|||
|
|
@ -19,6 +19,20 @@ sqincd sp
|
|||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Operands not matching up
|
||||
|
||||
sqincd x0, w1
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register
|
||||
// CHECK-NEXT: sqincd x0, w1
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
sqincd x0, x0
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
|
||||
// CHECK-NEXT: sqincd x0, x0
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Immediate not compatible with encode/decode function.
|
||||
|
||||
|
|
|
|||
|
|
@ -36,6 +36,47 @@ sqincd x0, all, mul #16
|
|||
// CHECK-UNKNOWN: e0 f3 ff 04 <unknown>
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------//
|
||||
// Test 32-bit form (x0, w0) and its aliases
|
||||
// ---------------------------------------------------------------------------//
|
||||
|
||||
sqincd x0, w0
|
||||
// CHECK-INST: sqincd x0, w0
|
||||
// CHECK-ENCODING: [0xe0,0xf3,0xe0,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 f3 e0 04 <unknown>
|
||||
|
||||
sqincd x0, w0, all
|
||||
// CHECK-INST: sqincd x0, w0
|
||||
// CHECK-ENCODING: [0xe0,0xf3,0xe0,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 f3 e0 04 <unknown>
|
||||
|
||||
sqincd x0, w0, all, mul #1
|
||||
// CHECK-INST: sqincd x0, w0
|
||||
// CHECK-ENCODING: [0xe0,0xf3,0xe0,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 f3 e0 04 <unknown>
|
||||
|
||||
sqincd x0, w0, all, mul #16
|
||||
// CHECK-INST: sqincd x0, w0, all
|
||||
// CHECK-ENCODING: [0xe0,0xf3,0xef,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 f3 ef 04 <unknown>
|
||||
|
||||
sqincd x0, w0, pow2
|
||||
// CHECK-INST: sqincd x0, w0, pow2
|
||||
// CHECK-ENCODING: [0x00,0xf0,0xe0,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 f0 e0 04 <unknown>
|
||||
|
||||
sqincd x0, w0, pow2, mul #16
|
||||
// CHECK-INST: sqincd x0, w0, pow2, mul #16
|
||||
// CHECK-ENCODING: [0x00,0xf0,0xef,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 f0 ef 04 <unknown>
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------//
|
||||
// Test all patterns for 64-bit form
|
||||
// ---------------------------------------------------------------------------//
|
||||
|
|
|
|||
|
|
@ -19,6 +19,20 @@ sqinch sp
|
|||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Operands not matching up
|
||||
|
||||
sqinch x0, w1
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register
|
||||
// CHECK-NEXT: sqinch x0, w1
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
sqinch x0, x0
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
|
||||
// CHECK-NEXT: sqinch x0, x0
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Immediate not compatible with encode/decode function.
|
||||
|
||||
|
|
|
|||
|
|
@ -36,6 +36,47 @@ sqinch x0, all, mul #16
|
|||
// CHECK-UNKNOWN: e0 f3 7f 04 <unknown>
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------//
|
||||
// Test 32-bit form (x0, w0) and its aliases
|
||||
// ---------------------------------------------------------------------------//
|
||||
|
||||
sqinch x0, w0
|
||||
// CHECK-INST: sqinch x0, w0
|
||||
// CHECK-ENCODING: [0xe0,0xf3,0x60,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 f3 60 04 <unknown>
|
||||
|
||||
sqinch x0, w0, all
|
||||
// CHECK-INST: sqinch x0, w0
|
||||
// CHECK-ENCODING: [0xe0,0xf3,0x60,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 f3 60 04 <unknown>
|
||||
|
||||
sqinch x0, w0, all, mul #1
|
||||
// CHECK-INST: sqinch x0, w0
|
||||
// CHECK-ENCODING: [0xe0,0xf3,0x60,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 f3 60 04 <unknown>
|
||||
|
||||
sqinch x0, w0, all, mul #16
|
||||
// CHECK-INST: sqinch x0, w0, all, mul #16
|
||||
// CHECK-ENCODING: [0xe0,0xf3,0x6f,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 f3 6f 04 <unknown>
|
||||
|
||||
sqinch x0, w0, pow2
|
||||
// CHECK-INST: sqinch x0, w0, pow2
|
||||
// CHECK-ENCODING: [0x00,0xf0,0x60,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 f0 60 04 <unknown>
|
||||
|
||||
sqinch x0, w0, pow2, mul #16
|
||||
// CHECK-INST: sqinch x0, w0, pow2, mul #16
|
||||
// CHECK-ENCODING: [0x00,0xf0,0x6f,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 f0 6f 04 <unknown>
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------//
|
||||
// Test all patterns for 64-bit form
|
||||
// ---------------------------------------------------------------------------//
|
||||
|
|
|
|||
|
|
@ -19,6 +19,20 @@ sqincw sp
|
|||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Operands not matching up
|
||||
|
||||
sqincw x0, w1
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register
|
||||
// CHECK-NEXT: sqincw x0, w1
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
sqincw x0, x0
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
|
||||
// CHECK-NEXT: sqincw x0, x0
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Immediate not compatible with encode/decode function.
|
||||
|
||||
|
|
|
|||
|
|
@ -36,6 +36,47 @@ sqincw x0, all, mul #16
|
|||
// CHECK-UNKNOWN: e0 f3 bf 04 <unknown>
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------//
|
||||
// Test 32-bit form (x0, w0) and its aliases
|
||||
// ---------------------------------------------------------------------------//
|
||||
|
||||
sqincw x0, w0
|
||||
// CHECK-INST: sqincw x0, w0
|
||||
// CHECK-ENCODING: [0xe0,0xf3,0xa0,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 f3 a0 04 <unknown>
|
||||
|
||||
sqincw x0, w0, all
|
||||
// CHECK-INST: sqincw x0, w0
|
||||
// CHECK-ENCODING: [0xe0,0xf3,0xa0,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 f3 a0 04 <unknown>
|
||||
|
||||
sqincw x0, w0, all, mul #1
|
||||
// CHECK-INST: sqincw x0, w0
|
||||
// CHECK-ENCODING: [0xe0,0xf3,0xa0,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 f3 a0 04 <unknown>
|
||||
|
||||
sqincw x0, w0, all, mul #16
|
||||
// CHECK-INST: sqincw x0, w0, all, mul #16
|
||||
// CHECK-ENCODING: [0xe0,0xf3,0xaf,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 f3 af 04 <unknown>
|
||||
|
||||
sqincw x0, w0, pow2
|
||||
// CHECK-INST: sqincw x0, w0, pow2
|
||||
// CHECK-ENCODING: [0x00,0xf0,0xa0,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 f0 a0 04 <unknown>
|
||||
|
||||
sqincw x0, w0, pow2, mul #16
|
||||
// CHECK-INST: sqincw x0, w0, pow2, mul #16
|
||||
// CHECK-ENCODING: [0x00,0xf0,0xaf,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 f0 af 04 <unknown>
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------//
|
||||
// Test all patterns for 64-bit form
|
||||
// ---------------------------------------------------------------------------//
|
||||
|
|
|
|||
|
|
@ -3,11 +3,6 @@
|
|||
// ------------------------------------------------------------------------- //
|
||||
// Invalid result register
|
||||
|
||||
uqdecb w0
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
|
||||
// CHECK-NEXT: uqdecb w0
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
uqdecb wsp
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
|
||||
// CHECK-NEXT: uqdecb wsp
|
||||
|
|
@ -19,6 +14,25 @@ uqdecb sp
|
|||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Operands not matching up (unsigned dec only has one register operand)
|
||||
|
||||
uqdecb x0, w0
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
|
||||
// CHECK-NEXT: uqdecb x0, w0
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
uqdecb w0, w0
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
|
||||
// CHECK-NEXT: uqdecb w0, w0
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
uqdecb x0, x0
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
|
||||
// CHECK-NEXT: uqdecb x0, x0
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Immediate not compatible with encode/decode function.
|
||||
|
||||
|
|
|
|||
|
|
@ -36,6 +36,47 @@ uqdecb x0, all, mul #16
|
|||
// CHECK-UNKNOWN: e0 ff 3f 04 <unknown>
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------//
|
||||
// Test 32-bit form (w0) and its aliases
|
||||
// ---------------------------------------------------------------------------//
|
||||
|
||||
uqdecb w0
|
||||
// CHECK-INST: uqdecb w0
|
||||
// CHECK-ENCODING: [0xe0,0xff,0x20,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 ff 20 04 <unknown>
|
||||
|
||||
uqdecb w0, all
|
||||
// CHECK-INST: uqdecb w0
|
||||
// CHECK-ENCODING: [0xe0,0xff,0x20,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 ff 20 04 <unknown>
|
||||
|
||||
uqdecb w0, all, mul #1
|
||||
// CHECK-INST: uqdecb w0
|
||||
// CHECK-ENCODING: [0xe0,0xff,0x20,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 ff 20 04 <unknown>
|
||||
|
||||
uqdecb w0, all, mul #16
|
||||
// CHECK-INST: uqdecb w0, all, mul #16
|
||||
// CHECK-ENCODING: [0xe0,0xff,0x2f,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 ff 2f 04 <unknown>
|
||||
|
||||
uqdecb w0, pow2
|
||||
// CHECK-INST: uqdecb w0, pow2
|
||||
// CHECK-ENCODING: [0x00,0xfc,0x20,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 fc 20 04 <unknown>
|
||||
|
||||
uqdecb w0, pow2, mul #16
|
||||
// CHECK-INST: uqdecb w0, pow2, mul #16
|
||||
// CHECK-ENCODING: [0x00,0xfc,0x2f,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 fc 2f 04 <unknown>
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------//
|
||||
// Test all patterns for 64-bit form
|
||||
// ---------------------------------------------------------------------------//
|
||||
|
|
|
|||
|
|
@ -3,11 +3,6 @@
|
|||
// ------------------------------------------------------------------------- //
|
||||
// Invalid result register
|
||||
|
||||
uqdecd w0
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
|
||||
// CHECK-NEXT: uqdecd w0
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
uqdecd wsp
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
|
||||
// CHECK-NEXT: uqdecd wsp
|
||||
|
|
@ -19,6 +14,25 @@ uqdecd sp
|
|||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Operands not matching up (unsigned dec only has one register operand)
|
||||
|
||||
uqdecd x0, w0
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
|
||||
// CHECK-NEXT: uqdecd x0, w0
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
uqdecd w0, w0
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
|
||||
// CHECK-NEXT: uqdecd w0, w0
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
uqdecd x0, x0
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
|
||||
// CHECK-NEXT: uqdecd x0, x0
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Immediate not compatible with encode/decode function.
|
||||
|
||||
|
|
|
|||
|
|
@ -36,6 +36,47 @@ uqdecd x0, all, mul #16
|
|||
// CHECK-UNKNOWN: e0 ff ff 04 <unknown>
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------//
|
||||
// Test 32-bit form (w0) and its aliases
|
||||
// ---------------------------------------------------------------------------//
|
||||
|
||||
uqdecd w0
|
||||
// CHECK-INST: uqdecd w0
|
||||
// CHECK-ENCODING: [0xe0,0xff,0xe0,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 ff e0 04 <unknown>
|
||||
|
||||
uqdecd w0, all
|
||||
// CHECK-INST: uqdecd w0
|
||||
// CHECK-ENCODING: [0xe0,0xff,0xe0,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 ff e0 04 <unknown>
|
||||
|
||||
uqdecd w0, all, mul #1
|
||||
// CHECK-INST: uqdecd w0
|
||||
// CHECK-ENCODING: [0xe0,0xff,0xe0,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 ff e0 04 <unknown>
|
||||
|
||||
uqdecd w0, all, mul #16
|
||||
// CHECK-INST: uqdecd w0, all, mul #16
|
||||
// CHECK-ENCODING: [0xe0,0xff,0xef,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 ff ef 04 <unknown>
|
||||
|
||||
uqdecd w0, pow2
|
||||
// CHECK-INST: uqdecd w0, pow2
|
||||
// CHECK-ENCODING: [0x00,0xfc,0xe0,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 fc e0 04 <unknown>
|
||||
|
||||
uqdecd w0, pow2, mul #16
|
||||
// CHECK-INST: uqdecd w0, pow2, mul #16
|
||||
// CHECK-ENCODING: [0x00,0xfc,0xef,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 fc ef 04 <unknown>
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------//
|
||||
// Test all patterns for 64-bit form
|
||||
// ---------------------------------------------------------------------------//
|
||||
|
|
|
|||
|
|
@ -3,11 +3,6 @@
|
|||
// ------------------------------------------------------------------------- //
|
||||
// Invalid result register
|
||||
|
||||
uqdech w0
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
|
||||
// CHECK-NEXT: uqdech w0
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
uqdech wsp
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
|
||||
// CHECK-NEXT: uqdech wsp
|
||||
|
|
@ -19,6 +14,25 @@ uqdech sp
|
|||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Operands not matching up (unsigned dec only has one register operand)
|
||||
|
||||
uqdech x0, w0
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
|
||||
// CHECK-NEXT: uqdech x0, w0
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
uqdech w0, w0
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
|
||||
// CHECK-NEXT: uqdech w0, w0
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
uqdech x0, x0
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
|
||||
// CHECK-NEXT: uqdech x0, x0
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Immediate not compatible with encode/decode function.
|
||||
|
||||
|
|
|
|||
|
|
@ -36,6 +36,47 @@ uqdech x0, all, mul #16
|
|||
// CHECK-UNKNOWN: e0 ff 7f 04 <unknown>
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------//
|
||||
// Test 32-bit form (w0) and its aliases
|
||||
// ---------------------------------------------------------------------------//
|
||||
|
||||
uqdech w0
|
||||
// CHECK-INST: uqdech w0
|
||||
// CHECK-ENCODING: [0xe0,0xff,0x60,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 ff 60 04 <unknown>
|
||||
|
||||
uqdech w0, all
|
||||
// CHECK-INST: uqdech w0
|
||||
// CHECK-ENCODING: [0xe0,0xff,0x60,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 ff 60 04 <unknown>
|
||||
|
||||
uqdech w0, all, mul #1
|
||||
// CHECK-INST: uqdech w0
|
||||
// CHECK-ENCODING: [0xe0,0xff,0x60,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 ff 60 04 <unknown>
|
||||
|
||||
uqdech w0, all, mul #16
|
||||
// CHECK-INST: uqdech w0, all, mul #16
|
||||
// CHECK-ENCODING: [0xe0,0xff,0x6f,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 ff 6f 04 <unknown>
|
||||
|
||||
uqdech w0, pow2
|
||||
// CHECK-INST: uqdech w0, pow2
|
||||
// CHECK-ENCODING: [0x00,0xfc,0x60,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 fc 60 04 <unknown>
|
||||
|
||||
uqdech w0, pow2, mul #16
|
||||
// CHECK-INST: uqdech w0, pow2, mul #16
|
||||
// CHECK-ENCODING: [0x00,0xfc,0x6f,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 fc 6f 04 <unknown>
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------//
|
||||
// Test all patterns for 64-bit form
|
||||
// ---------------------------------------------------------------------------//
|
||||
|
|
|
|||
|
|
@ -3,11 +3,6 @@
|
|||
// ------------------------------------------------------------------------- //
|
||||
// Invalid result register
|
||||
|
||||
uqdecw w0
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
|
||||
// CHECK-NEXT: uqdecw w0
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
uqdecw wsp
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
|
||||
// CHECK-NEXT: uqdecw wsp
|
||||
|
|
@ -19,6 +14,25 @@ uqdecw sp
|
|||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Operands not matching up (unsigned dec only has one register operand)
|
||||
|
||||
uqdecw x0, w0
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
|
||||
// CHECK-NEXT: uqdecw x0, w0
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
uqdecw w0, w0
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
|
||||
// CHECK-NEXT: uqdecw w0, w0
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
uqdecw x0, x0
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
|
||||
// CHECK-NEXT: uqdecw x0, x0
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Immediate not compatible with encode/decode function.
|
||||
|
||||
|
|
|
|||
|
|
@ -36,6 +36,47 @@ uqdecw x0, all, mul #16
|
|||
// CHECK-UNKNOWN: e0 ff bf 04 <unknown>
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------//
|
||||
// Test 32-bit form (w0) and its aliases
|
||||
// ---------------------------------------------------------------------------//
|
||||
|
||||
uqdecw w0
|
||||
// CHECK-INST: uqdecw w0
|
||||
// CHECK-ENCODING: [0xe0,0xff,0xa0,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 ff a0 04 <unknown>
|
||||
|
||||
uqdecw w0, all
|
||||
// CHECK-INST: uqdecw w0
|
||||
// CHECK-ENCODING: [0xe0,0xff,0xa0,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 ff a0 04 <unknown>
|
||||
|
||||
uqdecw w0, all, mul #1
|
||||
// CHECK-INST: uqdecw w0
|
||||
// CHECK-ENCODING: [0xe0,0xff,0xa0,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 ff a0 04 <unknown>
|
||||
|
||||
uqdecw w0, all, mul #16
|
||||
// CHECK-INST: uqdecw w0, all, mul #16
|
||||
// CHECK-ENCODING: [0xe0,0xff,0xaf,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 ff af 04 <unknown>
|
||||
|
||||
uqdecw w0, pow2
|
||||
// CHECK-INST: uqdecw w0, pow2
|
||||
// CHECK-ENCODING: [0x00,0xfc,0xa0,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 fc a0 04 <unknown>
|
||||
|
||||
uqdecw w0, pow2, mul #16
|
||||
// CHECK-INST: uqdecw w0, pow2, mul #16
|
||||
// CHECK-ENCODING: [0x00,0xfc,0xaf,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 fc af 04 <unknown>
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------//
|
||||
// Test all patterns for 64-bit form
|
||||
// ---------------------------------------------------------------------------//
|
||||
|
|
|
|||
|
|
@ -3,11 +3,6 @@
|
|||
// ------------------------------------------------------------------------- //
|
||||
// Invalid result register
|
||||
|
||||
uqincb w0
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
|
||||
// CHECK-NEXT: uqincb w0
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
uqincb wsp
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
|
||||
// CHECK-NEXT: uqincb wsp
|
||||
|
|
@ -19,6 +14,25 @@ uqincb sp
|
|||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Operands not matching up (unsigned inc only has one register operand)
|
||||
|
||||
uqincb x0, w0
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
|
||||
// CHECK-NEXT: uqincb x0, w0
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
uqincb w0, w0
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
|
||||
// CHECK-NEXT: uqincb w0, w0
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
uqincb x0, x0
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
|
||||
// CHECK-NEXT: uqincb x0, x0
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Immediate not compatible with encode/decode function.
|
||||
|
||||
|
|
|
|||
|
|
@ -36,6 +36,47 @@ uqincb x0, all, mul #16
|
|||
// CHECK-UNKNOWN: e0 f7 3f 04 <unknown>
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------//
|
||||
// Test 32-bit form (w0) and its aliases
|
||||
// ---------------------------------------------------------------------------//
|
||||
|
||||
uqincb w0
|
||||
// CHECK-INST: uqincb w0
|
||||
// CHECK-ENCODING: [0xe0,0xf7,0x20,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 f7 20 04 <unknown>
|
||||
|
||||
uqincb w0, all
|
||||
// CHECK-INST: uqincb w0
|
||||
// CHECK-ENCODING: [0xe0,0xf7,0x20,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 f7 20 04 <unknown>
|
||||
|
||||
uqincb w0, all, mul #1
|
||||
// CHECK-INST: uqincb w0
|
||||
// CHECK-ENCODING: [0xe0,0xf7,0x20,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 f7 20 04 <unknown>
|
||||
|
||||
uqincb w0, all, mul #16
|
||||
// CHECK-INST: uqincb w0, all, mul #16
|
||||
// CHECK-ENCODING: [0xe0,0xf7,0x2f,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 f7 2f 04 <unknown>
|
||||
|
||||
uqincb w0, pow2
|
||||
// CHECK-INST: uqincb w0, pow2
|
||||
// CHECK-ENCODING: [0x00,0xf4,0x20,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 f4 20 04 <unknown>
|
||||
|
||||
uqincb w0, pow2, mul #16
|
||||
// CHECK-INST: uqincb w0, pow2, mul #16
|
||||
// CHECK-ENCODING: [0x00,0xf4,0x2f,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 f4 2f 04 <unknown>
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------//
|
||||
// Test all patterns for 64-bit form
|
||||
// ---------------------------------------------------------------------------//
|
||||
|
|
|
|||
|
|
@ -3,11 +3,6 @@
|
|||
// ------------------------------------------------------------------------- //
|
||||
// Invalid result register
|
||||
|
||||
uqincd w0
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
|
||||
// CHECK-NEXT: uqincd w0
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
uqincd wsp
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
|
||||
// CHECK-NEXT: uqincd wsp
|
||||
|
|
@ -19,6 +14,25 @@ uqincd sp
|
|||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Operands not matching up (unsigned inc only has one register operand)
|
||||
|
||||
uqincd x0, w0
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
|
||||
// CHECK-NEXT: uqincd x0, w0
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
uqincd w0, w0
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
|
||||
// CHECK-NEXT: uqincd w0, w0
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
uqincd x0, x0
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
|
||||
// CHECK-NEXT: uqincd x0, x0
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Immediate not compatible with encode/decode function.
|
||||
|
||||
|
|
|
|||
|
|
@ -36,6 +36,47 @@ uqincd x0, all, mul #16
|
|||
// CHECK-UNKNOWN: e0 f7 ff 04 <unknown>
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------//
|
||||
// Test 32-bit form (w0) and its aliases
|
||||
// ---------------------------------------------------------------------------//
|
||||
|
||||
uqincd w0
|
||||
// CHECK-INST: uqincd w0
|
||||
// CHECK-ENCODING: [0xe0,0xf7,0xe0,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 f7 e0 04 <unknown>
|
||||
|
||||
uqincd w0, all
|
||||
// CHECK-INST: uqincd w0
|
||||
// CHECK-ENCODING: [0xe0,0xf7,0xe0,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 f7 e0 04 <unknown>
|
||||
|
||||
uqincd w0, all, mul #1
|
||||
// CHECK-INST: uqincd w0
|
||||
// CHECK-ENCODING: [0xe0,0xf7,0xe0,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 f7 e0 04 <unknown>
|
||||
|
||||
uqincd w0, all, mul #16
|
||||
// CHECK-INST: uqincd w0, all, mul #16
|
||||
// CHECK-ENCODING: [0xe0,0xf7,0xef,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 f7 ef 04 <unknown>
|
||||
|
||||
uqincd w0, pow2
|
||||
// CHECK-INST: uqincd w0, pow2
|
||||
// CHECK-ENCODING: [0x00,0xf4,0xe0,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 f4 e0 04 <unknown>
|
||||
|
||||
uqincd w0, pow2, mul #16
|
||||
// CHECK-INST: uqincd w0, pow2, mul #16
|
||||
// CHECK-ENCODING: [0x00,0xf4,0xef,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 f4 ef 04 <unknown>
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------//
|
||||
// Test all patterns for 64-bit form
|
||||
// ---------------------------------------------------------------------------//
|
||||
|
|
|
|||
|
|
@ -3,11 +3,6 @@
|
|||
// ------------------------------------------------------------------------- //
|
||||
// Invalid result register
|
||||
|
||||
uqinch w0
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
|
||||
// CHECK-NEXT: uqinch w0
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
uqinch wsp
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
|
||||
// CHECK-NEXT: uqinch wsp
|
||||
|
|
@ -19,6 +14,25 @@ uqinch sp
|
|||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Operands not matching up (unsigned inc only has one register operand)
|
||||
|
||||
uqinch x0, w0
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
|
||||
// CHECK-NEXT: uqinch x0, w0
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
uqinch w0, w0
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
|
||||
// CHECK-NEXT: uqinch w0, w0
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
uqinch x0, x0
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
|
||||
// CHECK-NEXT: uqinch x0, x0
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Immediate not compatible with encode/decode function.
|
||||
|
||||
|
|
|
|||
|
|
@ -36,6 +36,47 @@ uqinch x0, all, mul #16
|
|||
// CHECK-UNKNOWN: e0 f7 7f 04 <unknown>
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------//
|
||||
// Test 32-bit form (w0) and its aliases
|
||||
// ---------------------------------------------------------------------------//
|
||||
|
||||
uqinch w0
|
||||
// CHECK-INST: uqinch w0
|
||||
// CHECK-ENCODING: [0xe0,0xf7,0x60,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 f7 60 04 <unknown>
|
||||
|
||||
uqinch w0, all
|
||||
// CHECK-INST: uqinch w0
|
||||
// CHECK-ENCODING: [0xe0,0xf7,0x60,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 f7 60 04 <unknown>
|
||||
|
||||
uqinch w0, all, mul #1
|
||||
// CHECK-INST: uqinch w0
|
||||
// CHECK-ENCODING: [0xe0,0xf7,0x60,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 f7 60 04 <unknown>
|
||||
|
||||
uqinch w0, all, mul #16
|
||||
// CHECK-INST: uqinch w0, all, mul #16
|
||||
// CHECK-ENCODING: [0xe0,0xf7,0x6f,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 f7 6f 04 <unknown>
|
||||
|
||||
uqinch w0, pow2
|
||||
// CHECK-INST: uqinch w0, pow2
|
||||
// CHECK-ENCODING: [0x00,0xf4,0x60,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 f4 60 04 <unknown>
|
||||
|
||||
uqinch w0, pow2, mul #16
|
||||
// CHECK-INST: uqinch w0, pow2, mul #16
|
||||
// CHECK-ENCODING: [0x00,0xf4,0x6f,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 f4 6f 04 <unknown>
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------//
|
||||
// Test all patterns for 64-bit form
|
||||
// ---------------------------------------------------------------------------//
|
||||
|
|
|
|||
|
|
@ -3,11 +3,6 @@
|
|||
// ------------------------------------------------------------------------- //
|
||||
// Invalid result register
|
||||
|
||||
uqincw w0
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
|
||||
// CHECK-NEXT: uqincw w0
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
uqincw wsp
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
|
||||
// CHECK-NEXT: uqincw wsp
|
||||
|
|
@ -19,6 +14,25 @@ uqincw sp
|
|||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Operands not matching up (unsigned inc only has one register operand)
|
||||
|
||||
uqincw x0, w0
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
|
||||
// CHECK-NEXT: uqincw x0, w0
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
uqincw w0, w0
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
|
||||
// CHECK-NEXT: uqincw w0, w0
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
uqincw x0, x0
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
|
||||
// CHECK-NEXT: uqincw x0, x0
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Immediate not compatible with encode/decode function.
|
||||
|
||||
|
|
|
|||
|
|
@ -36,6 +36,47 @@ uqincw x0, all, mul #16
|
|||
// CHECK-UNKNOWN: e0 f7 bf 04 <unknown>
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------//
|
||||
// Test 32-bit form (w0) and its aliases
|
||||
// ---------------------------------------------------------------------------//
|
||||
|
||||
uqincw w0
|
||||
// CHECK-INST: uqincw w0
|
||||
// CHECK-ENCODING: [0xe0,0xf7,0xa0,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 f7 a0 04 <unknown>
|
||||
|
||||
uqincw w0, all
|
||||
// CHECK-INST: uqincw w0
|
||||
// CHECK-ENCODING: [0xe0,0xf7,0xa0,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 f7 a0 04 <unknown>
|
||||
|
||||
uqincw w0, all, mul #1
|
||||
// CHECK-INST: uqincw w0
|
||||
// CHECK-ENCODING: [0xe0,0xf7,0xa0,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 f7 a0 04 <unknown>
|
||||
|
||||
uqincw w0, all, mul #16
|
||||
// CHECK-INST: uqincw w0, all, mul #16
|
||||
// CHECK-ENCODING: [0xe0,0xf7,0xaf,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: e0 f7 af 04 <unknown>
|
||||
|
||||
uqincw w0, pow2
|
||||
// CHECK-INST: uqincw w0, pow2
|
||||
// CHECK-ENCODING: [0x00,0xf4,0xa0,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 f4 a0 04 <unknown>
|
||||
|
||||
uqincw w0, pow2, mul #16
|
||||
// CHECK-INST: uqincw w0, pow2, mul #16
|
||||
// CHECK-ENCODING: [0x00,0xf4,0xaf,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 f4 af 04 <unknown>
|
||||
|
||||
|
||||
// ---------------------------------------------------------------------------//
|
||||
// Test all patterns for 64-bit form
|
||||
// ---------------------------------------------------------------------------//
|
||||
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Reference in New Issue