From 7a6c37d3e7f6ed63e5bbe1c941744a156335fbc7 Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Fri, 17 Sep 2010 22:36:38 +0000 Subject: [PATCH] Teach the (non-MC) instruction printer to use the cannonical names for push/pop, and shift instructions on ARM. Update the tests to match. llvm-svn: 114230 --- llvm/lib/Target/ARM/ARMAsmPrinter.cpp | 75 ++++++++++++++++++- .../Target/ARM/AsmPrinter/ARMInstPrinter.cpp | 1 + .../CodeGen/ARM/2007-01-19-InfiniteLoop.ll | 2 +- llvm/test/CodeGen/ARM/ifcvt10.ll | 8 +- llvm/test/CodeGen/ARM/stm.ll | 5 +- llvm/test/CodeGen/Thumb2/large-stack.ll | 2 +- 6 files changed, 82 insertions(+), 11 deletions(-) diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp index 476b2533ffb1..cb57dcdead6f 100644 --- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp @@ -1147,11 +1147,78 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { OS << ']'; OS << "+"; printOperand(MI, NOps-2, OS); - OutStreamer.EmitRawText(OS.str()); - return; - } + } else if (MI->getOpcode() == ARM::MOVs) { + // FIXME: Thumb variants? + const MachineOperand &Dst = MI->getOperand(0); + const MachineOperand &MO1 = MI->getOperand(1); + const MachineOperand &MO2 = MI->getOperand(2); + const MachineOperand &MO3 = MI->getOperand(3); - printInstruction(MI, OS); + OS << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm())); + printSBitModifierOperand(MI, 6, OS); + printPredicateOperand(MI, 4, OS); + + OS << '\t' << getRegisterName(Dst.getReg()) + << ", " << getRegisterName(MO1.getReg()); + + if (ARM_AM::getSORegShOp(MO3.getImm()) != ARM_AM::rrx) { + OS << ", "; + + if (MO2.getReg()) { + OS << getRegisterName(MO2.getReg()); + assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0); + } else { + OS << "#" << ARM_AM::getSORegOffset(MO3.getImm()); + } + } + } else + // A8.6.123 PUSH + if ((MI->getOpcode() == ARM::STM_UPD || MI->getOpcode() == ARM::t2STM_UPD) && + MI->getOperand(0).getReg() == ARM::SP) { + const MachineOperand &MO1 = MI->getOperand(2); + if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) { + OS << '\t' << "push"; + printPredicateOperand(MI, 3, OS); + OS << '\t'; + printRegisterList(MI, 5, OS); + } + } else + // A8.6.122 POP + if ((MI->getOpcode() == ARM::LDM_UPD || MI->getOpcode() == ARM::t2LDM_UPD) && + MI->getOperand(0).getReg() == ARM::SP) { + const MachineOperand &MO1 = MI->getOperand(2); + if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) { + OS << '\t' << "pop"; + printPredicateOperand(MI, 3, OS); + OS << '\t'; + printRegisterList(MI, 5, OS); + } + } else + // A8.6.355 VPUSH + if ((MI->getOpcode() == ARM::VSTMS_UPD || MI->getOpcode() ==ARM::VSTMD_UPD) && + MI->getOperand(0).getReg() == ARM::SP) { + const MachineOperand &MO1 = MI->getOperand(2); + if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) { + OS << '\t' << "vpush"; + printPredicateOperand(MI, 3, OS); + OS << '\t'; + printRegisterList(MI, 5, OS); + } + } else + // A8.6.354 VPOP + if ((MI->getOpcode() == ARM::VLDMS_UPD || MI->getOpcode() ==ARM::VLDMD_UPD) && + MI->getOperand(0).getReg() == ARM::SP) { + const MachineOperand &MO1 = MI->getOperand(2); + if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) { + OS << '\t' << "vpop"; + printPredicateOperand(MI, 3, OS); + OS << '\t'; + printRegisterList(MI, 5, OS); + } + } else + printInstruction(MI, OS); + + // Output the instruction to the stream OutStreamer.EmitRawText(OS.str()); // Make sure the instruction that follows TBB is 2-byte aligned. diff --git a/llvm/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp b/llvm/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp index 4969d7ccb3f3..c15d457265ef 100644 --- a/llvm/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp +++ b/llvm/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp @@ -55,6 +55,7 @@ static unsigned getDPRSuperRegForSPR(unsigned Reg) { void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) { // Check for MOVs and print canonical forms, instead. if (MI->getOpcode() == ARM::MOVs) { + // FIXME: Thumb variants? const MCOperand &Dst = MI->getOperand(0); const MCOperand &MO1 = MI->getOperand(1); const MCOperand &MO2 = MI->getOperand(2); diff --git a/llvm/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll b/llvm/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll index ee63656b26d3..7f299aa1ceb2 100644 --- a/llvm/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll +++ b/llvm/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll @@ -9,7 +9,7 @@ define fastcc i32 @dct_luma_sp(i32 %block_x, i32 %block_y, i32* %coeff_cost) { entry: ; Make sure to use base-updating stores for saving callee-saved registers. ; CHECK-NOT: sub sp -; CHECK: vstmdb sp! +; CHECK: vpush %predicted_block = alloca [4 x [4 x i32]], align 4 ; <[4 x [4 x i32]]*> [#uses=1] br label %cond_next489 diff --git a/llvm/test/CodeGen/ARM/ifcvt10.ll b/llvm/test/CodeGen/ARM/ifcvt10.ll index e3bcf18ef4d7..57561eb65dde 100644 --- a/llvm/test/CodeGen/ARM/ifcvt10.ll +++ b/llvm/test/CodeGen/ARM/ifcvt10.ll @@ -12,10 +12,10 @@ define arm_aapcs_vfpcc float @aaa(%vec* nocapture %ustart, %vec* nocapture %udir ; CHECK: aaa: ; CHECK: vldr.32 ; CHECK-NOT: vldrne -; CHECK-NOT: vldmiane -; CHECK-NOT: ldmiane -; CHECK: vldmia sp! -; CHECK: ldmia sp! +; CHECK-NOT: vpopne +; CHECK-NOT: popne +; CHECK: vpop +; CHECK: pop entry: br i1 undef, label %bb81, label %bb48 diff --git a/llvm/test/CodeGen/ARM/stm.ll b/llvm/test/CodeGen/ARM/stm.ll index 22a7ecb4aa28..2f5fadbee28a 100644 --- a/llvm/test/CodeGen/ARM/stm.ll +++ b/llvm/test/CodeGen/ARM/stm.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6,+vfp2 | grep stm | count 2 +; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6,+vfp2 | FileCheck %s @"\01LC" = internal constant [32 x i8] c"Boolean Not: %d %d %d %d %d %d\0A\00", section "__TEXT,__cstring,cstring_literals" ; <[32 x i8]*> [#uses=1] @"\01LC1" = internal constant [26 x i8] c"Bitwise Not: %d %d %d %d\0A\00", section "__TEXT,__cstring,cstring_literals" ; <[26 x i8]*> [#uses=1] @@ -7,6 +7,9 @@ declare i32 @printf(i8* nocapture, ...) nounwind define i32 @main() nounwind { entry: +; CHECK: main +; CHECK: push +; CHECK: stmib %0 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([26 x i8]* @"\01LC1", i32 0, i32 0), i32 -2, i32 -3, i32 2, i32 -6) nounwind ; [#uses=0] %1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([32 x i8]* @"\01LC", i32 0, i32 0), i32 0, i32 1, i32 0, i32 1, i32 0, i32 1) nounwind ; [#uses=0] ret i32 0 diff --git a/llvm/test/CodeGen/Thumb2/large-stack.ll b/llvm/test/CodeGen/Thumb2/large-stack.ll index 97295341858c..763d316bdb7d 100644 --- a/llvm/test/CodeGen/Thumb2/large-stack.ll +++ b/llvm/test/CodeGen/Thumb2/large-stack.ll @@ -27,7 +27,7 @@ define i32 @test3() { ; DARWIN: sub.w sp, sp, #805306368 ; DARWIN: sub sp, #20 ; LINUX: test3: -; LINUX: stmdb sp!, {r4, r7, r11, lr} +; LINUX: push {r4, r7, r11, lr} ; LINUX: sub.w sp, sp, #805306368 ; LINUX: sub sp, #16 %retval = alloca i32, align 4