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[X86] Fix bug in COMISD and COMISS definition in td files 

COMISD should receive QWORD because it is defined as
 (V)COMISD xmm1, xmm2/m64

COMISS should receive DWORD because it is defined as
 (V)COMISS xmm1, xmm2/m32

Differential Revision: http://reviews.llvm.org/D11712

llvm-svn: 245551
This commit is contained in:
Marina Yatsina 2015-08-20 11:21:36 +00:00
parent 182227bd5b
commit 7a4e1ba737
4 changed files with 24 additions and 6 deletions
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4
llvm/lib/Target/X86/X86InstrAVX512.td
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@ -5045,10 +5045,10 @@ let Defs = [EFLAGS], Predicates = [HasAVX512] in {
"ucomisd">, PD, EVEX, "ucomisd">, PD, EVEX,
VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>; VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
let Pattern = []<dag> in { let Pattern = []<dag> in {
defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load, defm VCOMISSZ : sse12_ord_cmp<0x2F, FR32X, undef, f32, f32mem, loadf32,
"comiss">, PS, EVEX, VEX_LIG, "comiss">, PS, EVEX, VEX_LIG,
EVEX_CD8<32, CD8VT1>; EVEX_CD8<32, CD8VT1>;
defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load, defm VCOMISDZ : sse12_ord_cmp<0x2F, FR64X, undef, f64, f64mem, loadf64,
"comisd">, PD, EVEX, "comisd">, PD, EVEX,
VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>; VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
} }

8
llvm/lib/Target/X86/X86InstrSSE.td
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@ -2456,9 +2456,9 @@ let Defs = [EFLAGS] in {
defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64, defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
"ucomisd">, PD, VEX, VEX_LIG; "ucomisd">, PD, VEX, VEX_LIG;
let Pattern = []<dag> in { let Pattern = []<dag> in {
defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load, defm VCOMISS : sse12_ord_cmp<0x2F, FR32, undef, f32, f32mem, loadf32,
"comiss">, PS, VEX, VEX_LIG; "comiss">, PS, VEX, VEX_LIG;
defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load, defm VCOMISD : sse12_ord_cmp<0x2F, FR64, undef, f64, f64mem, loadf64,
"comisd">, PD, VEX, VEX_LIG; "comisd">, PD, VEX, VEX_LIG;
} }
@ -2479,9 +2479,9 @@ let Defs = [EFLAGS] in {
"ucomisd">, PD; "ucomisd">, PD;
let Pattern = []<dag> in { let Pattern = []<dag> in {
defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load, defm COMISS : sse12_ord_cmp<0x2F, FR32, undef, f32, f32mem, loadf32,
"comiss">, PS; "comiss">, PS;
defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load, defm COMISD : sse12_ord_cmp<0x2F, FR64, undef, f64, f64mem, loadf64,
"comisd">, PD; "comisd">, PD;
} }

8
llvm/test/MC/X86/intel-syntax-avx512.s
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@ -256,3 +256,11 @@ vaddpd zmm1,zmm1,zmm2,{rz-sae}
// CHECK: vfixupimmsd xmm13 , xmm26, qword ptr [rdx - 1032], 123 // CHECK: vfixupimmsd xmm13 , xmm26, qword ptr [rdx - 1032], 123
// CHECK: encoding: [0x62,0x73,0xad,0x00,0x55,0xaa,0xf8,0xfb,0xff,0xff,0x7b] // CHECK: encoding: [0x62,0x73,0xad,0x00,0x55,0xaa,0xf8,0xfb,0xff,0xff,0x7b]
vfixupimmsd xmm13,xmm26,QWORD PTR [rdx-0x408],0x7b vfixupimmsd xmm13,xmm26,QWORD PTR [rdx-0x408],0x7b
// CHECK: vcomisd xmm23, qword ptr [rcx]
// CHECK: encoding: [0x62,0xe1,0xfd,0x08,0x2f,0x39]
vcomisd xmm23, QWORD PTR [rcx]
// CHECK: vcomiss xmm16, dword ptr [rcx]
// CHECK: encoding: [0x62,0xe1,0x7c,0x08,0x2f,0x01]
vcomiss xmm16, DWORD PTR [rcx]

10
llvm/test/MC/X86/intel-syntax.s
View File

@ -704,3 +704,13 @@ repnz cmpsb
sal eax, 123 sal eax, 123
// CHECK: shll $123, %eax // CHECK: shll $123, %eax
comisd xmm0, QWORD PTR [eax]
comiss xmm0, DWORD PTR [eax]
vcomisd xmm0, QWORD PTR [eax]
vcomiss xmm0, DWORD PTR [eax]
// CHECK: comisd (%eax), %xmm0
// CHECK: comiss (%eax), %xmm0
// CHECK: vcomisd (%eax), %xmm0
// CHECK: vcomiss (%eax), %xmm0