forked from OSchip/llvm-project
[mips] Correct the predicates of sign extension instructions
And eliminate the duplication of those instructions for microMIPS32r6. llvm-svn: 331346
This commit is contained in:
Simon Dardis
parent
e14e591c93
commit
7a36495bf7
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@ -203,20 +203,6 @@ class LBU32_FM_MMR6 : MipsR6Inst {
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let Inst{15-0} = offset;
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}
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class SIGN_EXTEND_FM_MMR6<string instr_asm, bits<10> funct>
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: MMR6Arch<instr_asm> {
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bits<5> rd;
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bits<5> rt;
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bits<32> Inst;
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let Inst{31-26} = 0b000000;
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let Inst{25-21} = rd;
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let Inst{20-16} = rt;
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let Inst{15-6} = funct;
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let Inst{5-0} = 0b111100;
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}
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class PCREL19_FM_MMR6<bits<2> funct> : MipsR6Inst {
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bits<5> rt;
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bits<19> imm;
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@ -136,8 +136,6 @@ class OR_MMR6_ENC : ARITH_FM_MMR6<"or", 0x290>;
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class ORI_MMR6_ENC : ADDI_FM_MMR6<"ori", 0x14>;
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class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>;
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class SB16_MMR6_ENC : LOAD_STORE_FM_MM16<0x22>;
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class SEB_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seb", 0b0010101100>;
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class SEH_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seh", 0b0011101100>;
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class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>;
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class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>;
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class SH16_MMR6_ENC : LOAD_STORE_FM_MM16<0x2a>;
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@ -529,8 +527,6 @@ class AUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
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class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd, II_AUI>;
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class SEB_MMR6_DESC : SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>;
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class SEH_MMR6_DESC : SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>;
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class ALUIPC_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
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InstrItinClass Itin> : MMR6Arch<instr_asm> {
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dag OutOperandList = (outs GPROpnd:$rt);
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@ -1382,8 +1378,6 @@ def OR_MMR6 : StdMMR6Rel, OR_MMR6_DESC, OR_MMR6_ENC, ISA_MICROMIPS32R6;
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def ORI_MMR6 : StdMMR6Rel, ORI_MMR6_DESC, ORI_MMR6_ENC, ISA_MICROMIPS32R6;
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def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6;
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def SB16_MMR6 : StdMMR6Rel, SB16_MMR6_DESC, SB16_MMR6_ENC, ISA_MICROMIPS32R6;
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def SEB_MMR6 : StdMMR6Rel, SEB_MMR6_DESC, SEB_MMR6_ENC, ISA_MICROMIPS32R6;
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def SEH_MMR6 : StdMMR6Rel, SEH_MMR6_DESC, SEH_MMR6_ENC, ISA_MICROMIPS32R6;
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def SELEQZ_MMR6 : R6MMR6Rel, SELEQZ_MMR6_ENC, SELEQZ_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def SELNEZ_MMR6 : R6MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC,
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@ -1660,10 +1654,6 @@ def : MipsInstAlias<"xor $rs, $imm",
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def : MipsInstAlias<"not $rt, $rs",
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(NOR_MMR6 GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>,
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ISA_MICROMIPS32R6;
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def : MipsInstAlias<"seh $rd", (SEH_MMR6 GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
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ISA_MICROMIPS32R6;
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def : MipsInstAlias<"seb $rd", (SEB_MMR6 GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
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ISA_MICROMIPS32R6;
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def : MipsInstAlias<"lapc $rd, $imm",
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(ADDIUPC_MMR6 GPR32Opnd:$rd, simm19_lsl2:$imm)>,
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ISA_MICROMIPS32R6;
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@ -927,9 +927,9 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
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/// Sign Ext In Register Instructions.
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def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
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SEB_FM_MM<0x0ac>, ISA_MIPS32R2;
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SEB_FM_MM<0x0ac>, ISA_MICROMIPS;
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def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
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SEB_FM_MM<0x0ec>, ISA_MIPS32R2;
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SEB_FM_MM<0x0ec>, ISA_MICROMIPS;
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/// Word Swap Bytes Within Halfwords
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def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>,
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@ -1325,9 +1325,9 @@ let Predicates = [InMicroMips] in {
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(BEQ_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>,
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ISA_MICROMIPS;
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def : MipsInstAlias<"seh $rd", (SEH_MM GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
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ISA_MIPS32R2_NOT_32R6_64R6;
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ISA_MICROMIPS;
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def : MipsInstAlias<"seb $rd", (SEB_MM GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
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ISA_MIPS32R2_NOT_32R6_64R6;
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ISA_MICROMIPS;
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def : MipsInstAlias<"break", (BREAK_MM 0, 0), 1>, ISA_MICROMIPS;
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def : MipsInstAlias<"break $imm", (BREAK_MM uimm10:$imm, 0), 1>,
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ISA_MICROMIPS;
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@ -2285,13 +2285,13 @@ def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>,
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ISA_MIPS1_NOT_32R6_64R6;
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def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>,
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ISA_MIPS1_NOT_32R6_64R6;
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}
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/// Sign Ext In Register Instructions.
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def SEB : MMRel, StdMMR6Rel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
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SEB_FM<0x10, 0x20>, ISA_MIPS32R2;
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def SEH : MMRel, StdMMR6Rel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
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SEB_FM<0x18, 0x20>, ISA_MIPS32R2;
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}
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/// Count Leading
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def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd, II_CLZ>, CLO_FM<0x20>,
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@ -150,9 +150,13 @@ neg.d $f0, $f2 # CHECK: neg.d $f0, $f2 # encoding: [0x54,0x
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clz $9, $6 # CHECK: clz $9, $6 # encoding: [0x01,0x26,0x5b,0x3c]
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clo $9, $6 # CHECK: clo $9, $6 # encoding: [0x01,0x26,0x4b,0x3c]
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seb $9, $6 # CHECK: seb $9, $6 # encoding: [0x01,0x26,0x2b,0x3c]
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# CHECK-NEXT: # <MCInst #{{[0-9]+}} SEB_MM
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seb $9 # CHECK: seb $9, $9 # encoding: [0x01,0x29,0x2b,0x3c]
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# CHECK-NEXT: # <MCInst #{{[0-9]+}} SEB_MM
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seh $9, $6 # CHECK: seh $9, $6 # encoding: [0x01,0x26,0x3b,0x3c]
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# CHECK-NEXT: # <MCInst #{{[0-9]+}} SEH_MM
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seh $9 # CHECK: seh $9, $9 # encoding: [0x01,0x29,0x3b,0x3c]
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# CHECK-NEXT: # <MCInst #{{[0-9]+}} SEH_MM
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wsbh $9, $6 # CHECK: wsbh $9, $6 # encoding: [0x01,0x26,0x7b,0x3c]
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ext $9, $6, 3, 7 # CHECK: ext $9, $6, 3, 7 # encoding: [0x01,0x26,0x30,0xec]
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ins $9, $6, 3, 7 # CHECK: ins $9, $6, 3, 7 # encoding: [0x01,0x26,0x48,0xcc]
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@ -235,9 +235,13 @@ a:
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sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
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sdxc1 $f11,$10($14)
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seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20]
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# CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
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seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20]
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# CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
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seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20]
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# CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
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seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20]
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# CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
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sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
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sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
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sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
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@ -235,9 +235,13 @@ a:
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sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
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sdxc1 $f11,$10($14)
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seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20]
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# CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
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seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20]
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# CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
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seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20]
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# CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
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seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20]
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# CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
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sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
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sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
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sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
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@ -236,9 +236,13 @@ a:
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sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
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sdxc1 $f11,$10($14)
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seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20]
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# CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
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seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20]
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# CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
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seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20]
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# CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
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seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20]
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# CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
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sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
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sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
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sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
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@ -201,9 +201,13 @@ a:
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rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16]
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rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96]
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seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20]
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# CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
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seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20]
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# CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
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seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20]
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# CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
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seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20]
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# CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
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sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
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sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
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sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
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@ -305,9 +305,13 @@ a:
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sdr $11,-20423($12)
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sdxc1 $f11,$10($14)
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seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20]
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# CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
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seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20]
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# CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
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seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20]
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# CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
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seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20]
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# CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
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sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
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sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
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sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
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@ -299,9 +299,13 @@ a:
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sdr $11,-20423($12)
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sdxc1 $f11,$10($14)
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seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20]
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# CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
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seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20]
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# CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
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seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20]
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# CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
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seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20]
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# CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
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sh $14,-6704($15)
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sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
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# CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
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@ -300,9 +300,13 @@ a:
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sdr $11,-20423($12)
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sdxc1 $f11,$10($14)
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seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20]
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# CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
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seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20]
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# CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
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seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20]
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# CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
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seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20]
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# CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
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sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
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sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
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sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
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@ -239,10 +239,14 @@ a:
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selnez $2,$3,$4 # CHECK: selnez $2, $3, $4 # encoding: [0x00,0x64,0x10,0x37]
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selnez.d $f0, $f2, $f4 # CHECK: selnez.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x17]
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selnez.s $f0, $f2, $f4 # CHECK: selnez.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x17]
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seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20]
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seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20]
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seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20]
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seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20]
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seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20]
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# CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
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seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20]
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# CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
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seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20]
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# CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
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seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20]
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# CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
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sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
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sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
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sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
|
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|
|
|
|||
Loading…
Reference in New Issue