forked from OSchip/llvm-project
AMDGPU/SILoadStoreOptimizer: Make some functions const
Reviewers: arsenm, pendingchaos, rampitec Reviewed By: rampitec Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65316 llvm-svn: 367517
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@ -165,9 +165,9 @@ private:
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static unsigned getNewOpcode(const CombineInfo &CI);
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static std::pair<unsigned, unsigned> getSubRegIdxs(const CombineInfo &CI);
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const TargetRegisterClass *getTargetRegisterClass(const CombineInfo &CI);
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unsigned getOpcodeWidth(const MachineInstr &MI);
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InstClassEnum getInstClass(unsigned Opc);
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unsigned getRegs(unsigned Opc);
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unsigned getOpcodeWidth(const MachineInstr &MI) const;
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InstClassEnum getInstClass(unsigned Opc) const;
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unsigned getRegs(unsigned Opc) const;
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bool findMatchingInst(CombineInfo &CI);
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@ -394,7 +394,7 @@ bool SILoadStoreOptimizer::widthsFit(const GCNSubtarget &STM,
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}
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}
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unsigned SILoadStoreOptimizer::getOpcodeWidth(const MachineInstr &MI) {
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unsigned SILoadStoreOptimizer::getOpcodeWidth(const MachineInstr &MI) const {
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const unsigned Opc = MI.getOpcode();
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if (TII->isMUBUF(MI)) {
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@ -413,7 +413,7 @@ unsigned SILoadStoreOptimizer::getOpcodeWidth(const MachineInstr &MI) {
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}
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}
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InstClassEnum SILoadStoreOptimizer::getInstClass(unsigned Opc) {
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InstClassEnum SILoadStoreOptimizer::getInstClass(unsigned Opc) const {
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if (TII->isMUBUF(Opc)) {
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const int baseOpcode = AMDGPU::getMUBUFBaseOpcode(Opc);
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@ -464,7 +464,7 @@ InstClassEnum SILoadStoreOptimizer::getInstClass(unsigned Opc) {
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}
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}
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unsigned SILoadStoreOptimizer::getRegs(unsigned Opc) {
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unsigned SILoadStoreOptimizer::getRegs(unsigned Opc) const {
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if (TII->isMUBUF(Opc)) {
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unsigned result = 0;
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