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[RISCV] Remove Zvlsseg extension. 

This string no longer appears in the Vector Extension specification.
The segment load/store instructions are just part of the vector
instruction set.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D117724
This commit is contained in:
Craig Topper 2022-01-20 11:49:35 -08:00
parent e99835ffed
commit 7a275dc354
33 changed files with 576 additions and 625 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
clang/include/clang/Basic/RISCVVTypes.def
View File

@ -30,8 +30,8 @@
//
// - ElBits is the size of one element in bits (SEW).
//
// - NF is the number of fields (NFIELDS) used in the Zvlsseg instructions
// (TODO).
// - NF is the number of fields (NFIELDS) used in the Load/Store Segment
// instructions (TODO).
//
// - IsSigned is true for vectors of signed integer elements and
// for vectors of floating-point elements.

6
clang/include/clang/Basic/riscv_vector.td
View File

@ -215,10 +215,10 @@ class RVVBuiltin<string suffix, string prototype, string type_range,
// an automatic definition in header is emitted.
string HeaderCode = "";
// Sub extension of vector spec. Currently only support Zvlsseg.
// Sub extension of vector spec.
list<string> RequiredExtensions = [];
// Number of fields for Zvlsseg.
// Number of fields for Load/Store Segment instructions.
int NF = 1;
}
@ -1567,7 +1567,6 @@ defm vle32ff: RVVVLEFFBuiltin<["i", "f"]>;
defm vle64ff: RVVVLEFFBuiltin<["l", "d"]>;
// 7.8 Vector Load/Store Segment Instructions
let RequiredExtensions = ["Zvlsseg"] in {
defm : RVVUnitStridedSegLoad<"vlseg">;
defm : RVVUnitStridedSegLoadFF<"vlseg">;
defm : RVVStridedSegLoad<"vlsseg">;
@ -1577,7 +1576,6 @@ defm : RVVUnitStridedSegStore<"vsseg">;
defm : RVVStridedSegStore<"vssseg">;
defm : RVVIndexedSegStore<"vsuxseg">;
defm : RVVIndexedSegStore<"vsoxseg">;
}
// 12. Vector Integer Arithmetic Instructions
// 12.1. Vector Single-Width Integer Add and Subtract

2
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c
View File

@ -2,7 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v \
// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
// RUN: -disable-O0-optnone -emit-llvm %s \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h>

4
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c
View File

@ -2,12 +2,12 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -target-feature +zfh \
// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
// RUN: -disable-O0-optnone \
// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -target-feature +zfh \
// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
// RUN: -disable-O0-optnone \
// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s

4
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
View File

@ -2,12 +2,12 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -target-feature +zfh \
// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
// RUN: -disable-O0-optnone \
// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -target-feature +zfh \
// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
// RUN: -disable-O0-optnone \
// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s

2
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsseg.c
View File

@ -2,7 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v \
// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
// RUN: -disable-O0-optnone -emit-llvm %s \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h>

2
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c
View File

@ -2,7 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v \
// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
// RUN: -disable-O0-optnone -emit-llvm %s \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h>

2
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsoxseg.c
View File

@ -2,7 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v \
// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
// RUN: -disable-O0-optnone -emit-llvm %s \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h>

2
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsseg.c
View File

@ -2,7 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v \
// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
// RUN: -disable-O0-optnone -emit-llvm %s \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h>

2
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssseg.c
View File

@ -2,7 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v \
// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
// RUN: -disable-O0-optnone -emit-llvm %s \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h>

2
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsuxseg.c
View File

@ -2,7 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v \
// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
// RUN: -disable-O0-optnone -emit-llvm %s \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h>

2
clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c
View File

@ -2,7 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +zfh -target-feature +experimental-v \
// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
// RUN: -disable-O0-optnone -emit-llvm %s \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h>

4
clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
View File

@ -2,12 +2,12 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -target-feature +zfh \
// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
// RUN: -disable-O0-optnone \
// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -target-feature +zfh \
// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
// RUN: -disable-O0-optnone \
// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s

4
clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c
View File

@ -2,12 +2,12 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -target-feature +zfh \
// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
// RUN: -disable-O0-optnone \
// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -target-feature +zfh \
// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
// RUN: -disable-O0-optnone \
// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s

2
clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c
View File

@ -2,7 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +zfh -target-feature +experimental-v \
// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
// RUN: -disable-O0-optnone -emit-llvm %s \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h>

2
clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c
View File

@ -2,7 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +zfh -target-feature +experimental-v \
// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
// RUN: -disable-O0-optnone -emit-llvm %s \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h>

2
clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxseg.c
View File

@ -2,7 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +zfh -target-feature +experimental-v \
// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
// RUN: -disable-O0-optnone -emit-llvm %s \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h>

2
clang/test/CodeGen/RISCV/rvv-intrinsics/vsseg.c
View File

@ -2,7 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +zfh -target-feature +experimental-v \
// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
// RUN: -disable-O0-optnone -emit-llvm %s \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h>

2
clang/test/CodeGen/RISCV/rvv-intrinsics/vssseg.c
View File

@ -2,7 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +zfh -target-feature +experimental-v \
// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
// RUN: -disable-O0-optnone -emit-llvm %s \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h>

2
clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxseg.c
View File

@ -2,7 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +zfh -target-feature +experimental-v \
// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
// RUN: -disable-O0-optnone -emit-llvm %s \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h>

19
clang/test/Driver/riscv-arch.c
View File

@ -416,25 +416,6 @@
// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-V-GOODVERS %s
// RV32-EXPERIMENTAL-V-GOODVERS: "-target-feature" "+experimental-v"
// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p10_zvlsseg -### %s -c 2>&1 | \
// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-NOFLAG %s
// RV32-EXPERIMENTAL-ZVLSSEG-NOFLAG: error: invalid arch name 'rv32iv0p10_zvlsseg'
// RV32-EXPERIMENTAL-ZVLSSEG-NOFLAG: requires '-menable-experimental-extensions'
// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p10_zvlsseg -menable-experimental-extensions -### %s -c 2>&1 | \
// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-NOVERS %s
// RV32-EXPERIMENTAL-ZVLSSEG-NOVERS: error: invalid arch name 'rv32iv0p10_zvlsseg'
// RV32-EXPERIMENTAL-ZVLSSEG-NOVERS: experimental extension requires explicit version number
// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p10_zvlsseg0p1 -menable-experimental-extensions -### %s -c 2>&1 | \
// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-BADVERS %s
// RV32-EXPERIMENTAL-ZVLSSEG-BADVERS: error: invalid arch name 'rv32iv0p10_zvlsseg0p1'
// RV32-EXPERIMENTAL-ZVLSSEG-BADVERS: unsupported version number 0.1 for experimental extension 'zvlsseg'
// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p10_zvlsseg0p10 -menable-experimental-extensions -### %s -c 2>&1 | \
// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-GOODVERS %s
// RV32-EXPERIMENTAL-ZVLSSEG-GOODVERS: "-target-feature" "+experimental-zvlsseg"
// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p10_zvl32b0p10 -### %s -c 2>&1 | \
// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVL-NOFLAG %s
// RV32-EXPERIMENTAL-ZVL-NOFLAG: error: invalid arch name 'rv32iv0p10_zvl32b0p10'

2
clang/test/Preprocessor/riscv-target-features.c
View File

@ -31,7 +31,6 @@
// CHECK-NOT: __riscv_zfh
// CHECK-NOT: __riscv_v
// CHECK-NOT: __riscv_vector
// CHECK-NOT: __riscv_zvlsseg
// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
@ -220,7 +219,6 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
// CHECK-V-EXT: __riscv_v 10000{{$}}
// CHECK-V-EXT: __riscv_vector 1
// CHECK-V-EXT: __riscv_zvlsseg 10000{{$}}
// RUN: %clang -target riscv32-unknown-linux-gnu \
// RUN: -march=rv32izfhmin1p0 -x c -E -dM %s \

11
clang/utils/TableGen/RISCVVEmitter.cpp
View File

@ -140,8 +140,7 @@ enum RISCVExtension : uint8_t {
F = 1 << 1,
D = 1 << 2,
Zfh = 1 << 3,
Zvlsseg = 1 << 4,
RV64 = 1 << 5,
RV64 = 1 << 4,
};
// TODO refactor RVVIntrinsic class design after support all intrinsic
@ -445,8 +444,8 @@ void RVVType::initBuiltinStr() {
return;
}
BuiltinStr = "q" + utostr(Scale.getValue()) + BuiltinStr;
// Pointer to vector types. Defined for Zvlsseg load intrinsics.
// Zvlsseg load intrinsics have pointer type arguments to store the loaded
// Pointer to vector types. Defined for segment load intrinsics.
// segment load intrinsics have pointer type arguments to store the loaded
// vector values.
if (IsPointer)
BuiltinStr += "*";
@ -797,8 +796,6 @@ RVVIntrinsic::RVVIntrinsic(StringRef NewName, StringRef Suffix,
RISCVExtensions |= RISCVExtension::D;
}
for (auto Extension : RequiredExtensions) {
if (Extension == "Zvlsseg")
RISCVExtensions |= RISCVExtension::Zvlsseg;
if (Extension == "RV64")
RISCVExtensions |= RISCVExtension::RV64;
}
@ -1311,8 +1308,6 @@ bool RVVEmitter::emitExtDefStr(uint8_t Extents, raw_ostream &OS) {
OS << LS << "defined(__riscv_d)";
if (Extents & RISCVExtension::Zfh)
OS << LS << "defined(__riscv_zfh)";
if (Extents & RISCVExtension::Zvlsseg)
OS << LS << "defined(__riscv_zvlsseg)";
if (Extents & RISCVExtension::RV64)
OS << LS << "(__riscv_xlen == 64)";
OS << "\n";

13
llvm/lib/Support/RISCVISAInfo.cpp
View File

@ -66,7 +66,6 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
{"zbr", RISCVExtensionVersion{0, 93}},
{"zbt", RISCVExtensionVersion{0, 93}},
{"zvlsseg", RISCVExtensionVersion{0, 10}},
{"zvl32b", RISCVExtensionVersion{0, 10}},
{"zvl64b", RISCVExtensionVersion{0, 10}},
{"zvl128b", RISCVExtensionVersion{0, 10}},
@ -301,9 +300,7 @@ void RISCVISAInfo::toFeatures(
if (ExtName == "i")
continue;
if (ExtName == "zvlsseg") {
Features.push_back("+experimental-zvlsseg");
} else if (isExperimentalExtension(ExtName)) {
if (isExperimentalExtension(ExtName)) {
Features.push_back(StrAlloc("+experimental-" + ExtName));
} else {
Features.push_back(StrAlloc("+" + ExtName));
@ -691,7 +688,6 @@ Error RISCVISAInfo::checkDependency() {
bool HasE = Exts.count("e") == 1;
bool HasD = Exts.count("d") == 1;
bool HasF = Exts.count("f") == 1;
bool HasZvlsseg = Exts.count("zvlsseg") == 1;
bool HasVector = Exts.count("zve32x") == 1;
bool HasZve32f = Exts.count("zve32f") == 1;
bool HasZve64d = Exts.count("zve64d") == 1;
@ -710,11 +706,6 @@ Error RISCVISAInfo::checkDependency() {
return createStringError(errc::invalid_argument,
"d requires f extension to also be specified");
if (HasZvlsseg && !HasVector)
return createStringError(
errc::invalid_argument,
"zvlsseg requires v or zve* extension to also be specified");
// FIXME: Consider Zfinx in the future
if (HasZve32f && !HasF)
return createStringError(
@ -745,7 +736,7 @@ static const char *ImpliedExtsZve64d[] = {"zve64f"};
static const char *ImpliedExtsZve64f[] = {"zve64x", "zve32f"};
static const char *ImpliedExtsZve64x[] = {"zve32x", "zvl64b"};
static const char *ImpliedExtsZve32f[] = {"zve32x"};
static const char *ImpliedExtsZve32x[] = {"zvlsseg", "zvl32b"};
static const char *ImpliedExtsZve32x[] = {"zvl32b"};
static const char *ImpliedExtsZvl65536b[] = {"zvl32768b"};
static const char *ImpliedExtsZvl32768b[] = {"zvl16384b"};
static const char *ImpliedExtsZvl16384b[] = {"zvl8192b"};

10
llvm/lib/Target/RISCV/RISCV.td
View File

@ -161,19 +161,11 @@ foreach i = { 6-15 } in {
[!cast<SubtargetFeature>("FeatureStdExtZvl"#!srl(I, 1)#"b")]>;
}
def FeatureStdExtZvlsseg
: SubtargetFeature<"experimental-zvlsseg", "HasStdExtZvlsseg", "true",
"'Zvlsseg' (Vector segment load/store instructions)",
[]>;
def HasStdExtZvlsseg : Predicate<"Subtarget->hasStdExtZvlsseg()">,
AssemblerPredicate<(all_of FeatureStdExtZvlsseg),
"'Zvlsseg' (Vector segment load/store instructions)">;
def FeatureStdExtZve32x
: SubtargetFeature<"experimental-zve32x", "HasStdExtZve32x", "true",
"'Zve32x' (Vector Extensions for Embedded Processors "
"with maximal 32 EEW)",
[FeatureStdExtZvlsseg, FeatureStdExtZvl32b]>;
[FeatureStdExtZvl32b]>;
def HasStdExtZve32x : Predicate<"SubTarget->hasStdExtZve32x()">,
AssemblerPredicate<(all_of FeatureStdExtZve32x),
"'Zve32x' (Vector Extensions for Embedded Processors "

12
llvm/lib/Target/RISCV/RISCVInstrInfoV.td
View File

@ -1461,7 +1461,7 @@ foreach n = [2, 4, 8] in {
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
} // Predicates = [HasVInstructions]
let Predicates = [HasStdExtZvlsseg] in {
let Predicates = [HasVInstructions] in {
foreach nf=2-8 in {
foreach eew = [8, 16, 32] in {
defvar w = !cast<RISCVWidth>("LSWidth"#eew);
@ -1494,9 +1494,9 @@ let Predicates = [HasStdExtZvlsseg] in {
"vsoxseg"#nf#"ei"#eew#".v">;
}
}
} // Predicates = [HasStdExtZvlsseg]
} // Predicates = [HasVInstructions]
let Predicates = [HasStdExtZvlsseg, HasVInstructionsI64] in {
let Predicates = [HasVInstructionsI64] in {
foreach nf=2-8 in {
// Vector Unit-strided Segment Instructions
def VLSEG#nf#E64_V :
@ -1512,8 +1512,8 @@ let Predicates = [HasStdExtZvlsseg, HasVInstructionsI64] in {
def VSSSEG#nf#E64_V :
VStridedSegmentStore<!add(nf, -1), LSWidth64, "vssseg"#nf#"e64.v">;
}
} // Predicates = [HasStdExtZvlsseg, HasVInstructionsI64]
let Predicates = [HasStdExtZvlsseg, HasVInstructionsI64, IsRV64] in {
} // Predicates = [HasVInstructionsI64]
let Predicates = [HasVInstructionsI64, IsRV64] in {
foreach nf=2-8 in {
// Vector Indexed Segment Instructions
def VLUXSEG#nf#EI64_V :
@ -1529,6 +1529,6 @@ let Predicates = [HasStdExtZvlsseg, HasVInstructionsI64, IsRV64] in {
VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder, LSWidth64,
"vsoxseg"#nf#"ei64.v">;
}
} // Predicates = [HasStdExtZvlsseg, HasVInstructionsI64, IsRV64]
} // Predicates = [HasVInstructionsI64, IsRV64]
include "RISCVInstrInfoVPseudos.td"

2
llvm/lib/Target/RISCV/RISCVSchedRocket.td
View File

@ -17,7 +17,7 @@ def RocketModel : SchedMachineModel {
let LoadLatency = 3;
let MispredictPenalty = 3;
let CompleteModel = false;
let UnsupportedFeatures = [HasStdExtV, HasVInstructions, HasVInstructionsI64, HasStdExtZvlsseg];
let UnsupportedFeatures = [HasStdExtV, HasVInstructions, HasVInstructionsI64];
}
//===----------------------------------------------------------------------===//

2
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
View File

@ -15,7 +15,7 @@ def SiFive7Model : SchedMachineModel {
let LoadLatency = 3;
let MispredictPenalty = 3;
let CompleteModel = 0;
let UnsupportedFeatures = [HasStdExtV, HasStdExtZvlsseg];
let UnsupportedFeatures = [HasStdExtV];
}
// The SiFive7 microarchitecture has two pipelines: A and B.

2
llvm/lib/Target/RISCV/RISCVSubtarget.h
View File

@ -81,7 +81,6 @@ private:
bool HasStdExtZve64x = false;
bool HasStdExtZve64f = false;
bool HasStdExtZve64d = false;
bool HasStdExtZvlsseg = false;
bool HasStdExtZfhmin = false;
bool HasStdExtZfh = false;
bool HasRV64 = false;
@ -160,7 +159,6 @@ public:
bool hasStdExtZve64x() const { return HasStdExtZve64x; }
bool hasStdExtZve64f() const { return HasStdExtZve64f; }
bool hasStdExtZve64d() const { return HasStdExtZve64d; }
bool hasStdExtZvlsseg() const { return HasStdExtZvlsseg; }
bool hasStdExtZvl() const { return ZvlLen != ExtZvl::NotSet; }
bool hasStdExtZfhmin() const { return HasStdExtZfhmin; }
bool hasStdExtZfh() const { return HasStdExtZfh; }

12
llvm/test/CodeGen/RISCV/attributes.ll
View File

@ -18,7 +18,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV32ZBT %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v %s -o - | FileCheck --check-prefix=RV32V %s
; RUN: llc -mtriple=riscv32 -mattr=+zbb,+zfh,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
; RUN: llc -mtriple=riscv32 -mattr=+zbb,+zfh,+experimental-v,+f %s -o - | FileCheck --check-prefix=RV32COMBINED %s
; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s
@ -37,7 +37,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+zbs %s -o - | FileCheck --check-prefix=RV64ZBS %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV64ZBT %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v %s -o - | FileCheck --check-prefix=RV64V %s
; RUN: llc -mtriple=riscv64 -mattr=+zbb,+zfh,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV64COMBINED %s
; RUN: llc -mtriple=riscv64 -mattr=+zbb,+zfh,+experimental-v,+f %s -o - | FileCheck --check-prefix=RV64COMBINED %s
; RV32M: .attribute 5, "rv32i2p0_m2p0"
@ -57,8 +57,8 @@
; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93"
; RV32ZBS: .attribute 5, "rv32i2p0_zbs1p0"
; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93"
; RV32V: .attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zfh1p0_zfhmin1p0_zbb1p0_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
; RV32V: .attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zfh1p0_zfhmin1p0_zbb1p0_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
; RV64M: .attribute 5, "rv64i2p0_m2p0"
; RV64A: .attribute 5, "rv64i2p0_a2p0"
@ -77,8 +77,8 @@
; RV64ZBR: .attribute 5, "rv64i2p0_zbr0p93"
; RV64ZBS: .attribute 5, "rv64i2p0_zbs1p0"
; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93"
; RV64V: .attribute 5, "rv64i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_d2p0_v0p10_zfh1p0_zfhmin1p0_zbb1p0_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
; RV64V: .attribute 5, "rv64i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_d2p0_v0p10_zfh1p0_zfhmin1p0_zbb1p0_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
define i32 @addi(i32 %a) {
%1 = add i32 %a, 1

4
llvm/test/MC/RISCV/attribute-arch-invalid.s
View File

@ -26,5 +26,5 @@
.attribute arch, "rv32izbt"
# CHECK: error: invalid arch name 'rv32izbt', experimental extension requires explicit version number `zbt`
.attribute arch, "rv32ivzvlsseg"
# CHECK: error: invalid arch name 'rv32ivzvlsseg', experimental extension requires explicit version number `v`
.attribute arch, "rv32iv"
# CHECK: error: invalid arch name 'rv32iv', experimental extension requires explicit version number `v`

40
llvm/test/MC/RISCV/attribute-arch.s
View File

@ -36,7 +36,7 @@
## Experimental extensions require version string to be explicitly specified
.attribute arch, "rv32iv0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
.attribute arch, "rv32izba1p0"
# CHECK: attribute 5, "rv32i2p0_zba1p0"
@ -74,56 +74,56 @@
.attribute arch, "rv32ifzfh1p0"
# CHECK: attribute 5, "rv32i2p0_f2p0_zfh1p0_zfhmin1p0"
.attribute arch, "rv32iv0p10zvlsseg0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
.attribute arch, "rv32iv0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
.attribute arch, "rv32iv0p10zvl32b0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
.attribute arch, "rv32iv0p10zvl64b0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
.attribute arch, "rv32iv0p10zvl128b0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
.attribute arch, "rv32iv0p10zvl256b0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10"
.attribute arch, "rv32iv0p10zvl512b0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10"
.attribute arch, "rv32iv0p10zvl1024b0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10"
.attribute arch, "rv32iv0p10zvl2048b0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10"
.attribute arch, "rv32iv0p10zvl4096b0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10"
.attribute arch, "rv32iv0p10zvl8192b0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10"
.attribute arch, "rv32iv0p10zvl16384b0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10"
.attribute arch, "rv32iv0p10zvl32768b0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10"
.attribute arch, "rv32iv0p10zvl65536b0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl65536b0p10_zvl8192b0p10_zvlsseg0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl65536b0p10_zvl8192b0p10"
.attribute arch, "rv32i_zve32x0p10"
# CHECK: attribute 5, "rv32i2p0_zve32x0p10_zvl32b0p10_zvlsseg0p10"
# CHECK: attribute 5, "rv32i2p0_zve32x0p10_zvl32b0p10"
.attribute arch, "rv32if_zve32f0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_zve32f0p10_zve32x0p10_zvl32b0p10_zvlsseg0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_zve32f0p10_zve32x0p10_zvl32b0p10"
.attribute arch, "rv32i_zve64x0p10"
# CHECK: attribute 5, "rv32i2p0_zve32x0p10_zve64x0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
# CHECK: attribute 5, "rv32i2p0_zve32x0p10_zve64x0p10_zvl32b0p10_zvl64b0p10"
.attribute arch, "rv32if_zve64f0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_zve32f0p10_zve32x0p10_zve64f0p10_zve64x0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_zve32f0p10_zve32x0p10_zve64f0p10_zve64x0p10_zvl32b0p10_zvl64b0p10"
.attribute arch, "rv32ifd_zve64d0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl32b0p10_zvl64b0p10"

1018
llvm/test/MC/RISCV/rvv/zvlsseg.s
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