forked from OSchip/llvm-project
[GlobalISel][AArch64] Add support for base register + offset register loads
Add support for folding G_GEPs into loads of the form ``` ldr reg, [base, off] ``` when possible. This can save an add before the load. Currently, this is only supported for loads of 64 bits into 64 bit registers. Add a new addressing mode function, `selectAddrModeRegisterOffset` which performs this folding when it is profitable. Also add a test for addressing modes for G_LOAD. Differential Revision: https://reviews.llvm.org/D64944 llvm-svn: 366503
This commit is contained in:
Jessica Paquette
parent
50057f3288
commit
7a1dcc5ff1
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@ -67,6 +67,7 @@ private:
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bool earlySelect(MachineInstr &I) const;
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bool earlySelectSHL(MachineInstr &I, MachineRegisterInfo &MRI) const;
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bool earlySelectLoad(MachineInstr &I, MachineRegisterInfo &MRI) const;
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bool selectVaStartAAPCS(MachineInstr &I, MachineFunction &MF,
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MachineRegisterInfo &MRI) const;
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@ -182,6 +183,7 @@ private:
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ComplexRendererFns selectAddrModeIndexed(MachineOperand &Root) const {
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return selectAddrModeIndexed(Root, Width / 8);
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}
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ComplexRendererFns selectAddrModeRegisterOffset(MachineOperand &Root) const;
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void renderTruncImm(MachineInstrBuilder &MIB, const MachineInstr &MI) const;
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@ -1158,6 +1160,57 @@ bool AArch64InstructionSelector::earlySelectSHL(
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return constrainSelectedInstRegOperands(*NewI, TII, TRI, RBI);
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}
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bool AArch64InstructionSelector::earlySelectLoad(
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MachineInstr &I, MachineRegisterInfo &MRI) const {
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// Try to fold in shifts, etc into the addressing mode of a load.
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assert(I.getOpcode() == TargetOpcode::G_LOAD && "unexpected op");
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// Don't handle atomic loads/stores yet.
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auto &MemOp = **I.memoperands_begin();
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if (MemOp.getOrdering() != AtomicOrdering::NotAtomic) {
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LLVM_DEBUG(dbgs() << "Atomic load/store not supported yet\n");
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return false;
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}
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unsigned MemBytes = MemOp.getSize();
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// Only support 64-bit loads for now.
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if (MemBytes != 8)
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return false;
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Register DstReg = I.getOperand(0).getReg();
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const LLT DstTy = MRI.getType(DstReg);
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// Don't handle vectors.
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if (DstTy.isVector())
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return false;
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unsigned DstSize = DstTy.getSizeInBits();
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// TODO: 32-bit destinations.
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if (DstSize != 64)
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return false;
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// Check if we can do any folding from GEPs etc. into the load.
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auto ImmFn = selectAddrModeRegisterOffset(I.getOperand(1));
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if (!ImmFn)
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return false;
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// We can fold something. Emit the load here.
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MachineIRBuilder MIB(I);
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// Choose the instruction based off the size of the element being loaded, and
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// whether or not we're loading into a FPR.
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const RegisterBank &RB = *RBI.getRegBank(DstReg, MRI, TRI);
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unsigned Opc =
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RB.getID() == AArch64::GPRRegBankID ? AArch64::LDRXroX : AArch64::LDRDroX;
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// Construct the load.
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auto LoadMI = MIB.buildInstr(Opc, {DstReg}, {});
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for (auto &RenderFn : *ImmFn)
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RenderFn(LoadMI);
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LoadMI.addMemOperand(*I.memoperands_begin());
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I.eraseFromParent();
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return constrainSelectedInstRegOperands(*LoadMI, TII, TRI, RBI);
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}
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bool AArch64InstructionSelector::earlySelect(MachineInstr &I) const {
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assert(I.getParent() && "Instruction should be in a basic block!");
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assert(I.getParent()->getParent() && "Instruction should be in a function!");
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@ -1169,6 +1222,8 @@ bool AArch64InstructionSelector::earlySelect(MachineInstr &I) const {
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switch (I.getOpcode()) {
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case TargetOpcode::G_SHL:
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return earlySelectSHL(I, MRI);
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case TargetOpcode::G_LOAD:
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return earlySelectLoad(I, MRI);
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default:
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return false;
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}
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@ -3891,6 +3946,44 @@ AArch64InstructionSelector::selectArithImmed(MachineOperand &Root) const {
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}};
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}
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/// This is used for computing addresses like this:
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///
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/// ldr x1, [x2, x3]
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///
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/// Where x2 is the base register, and x3 is an offset register.
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///
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/// When possible (or profitable) to fold a G_GEP into the address calculation,
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/// this will do so. Otherwise, it will return None.
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InstructionSelector::ComplexRendererFns
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AArch64InstructionSelector::selectAddrModeRegisterOffset(
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MachineOperand &Root) const {
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MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo();
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// If we have a constant offset, then we probably don't want to match a
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// register offset.
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if (isBaseWithConstantOffset(Root, MRI))
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return None;
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// We need a GEP.
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MachineInstr *Gep = MRI.getVRegDef(Root.getReg());
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if (!Gep || Gep->getOpcode() != TargetOpcode::G_GEP)
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return None;
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// If this is used more than once, let's not bother folding.
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// TODO: Check if they are memory ops. If they are, then we can still fold
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// without having to recompute anything.
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if (!MRI.hasOneUse(Gep->getOperand(0).getReg()))
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return None;
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// Base is the GEP's LHS, offset is its RHS.
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return {{
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[=](MachineInstrBuilder &MIB) { MIB.add(Gep->getOperand(1)); },
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[=](MachineInstrBuilder &MIB) { MIB.add(Gep->getOperand(2)); },
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[=](MachineInstrBuilder &MIB) { MIB.addImm(0); },
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[=](MachineInstrBuilder &MIB) { MIB.addImm(0); },
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}};
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}
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/// Select a "register plus unscaled signed 9-bit immediate" address. This
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/// should only match when there is an offset that is not valid for a scaled
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/// immediate addressing mode. The "Size" argument is the size in bytes of the
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@ -0,0 +1,90 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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--- |
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define void @ldrxrox_breg_oreg(i64* %addr) { ret void }
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define void @ldrdrox_breg_oreg(i64* %addr) { ret void }
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define void @more_than_one_use(i64* %addr) { ret void }
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...
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---
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name: ldrxrox_breg_oreg
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $x0, $x1
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; CHECK-LABEL: name: ldrxrox_breg_oreg
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; CHECK: liveins: $x0, $x1
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
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; CHECK: [[LDRXroX:%[0-9]+]]:gpr64 = LDRXroX [[COPY]], [[COPY1]], 0, 0 :: (load 8 from %ir.addr)
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; CHECK: $x0 = COPY [[LDRXroX]]
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; CHECK: RET_ReallyLR implicit $x0
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%0:gpr(p0) = COPY $x0
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%1:gpr(s64) = COPY $x1
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%2:gpr(p0) = G_GEP %0, %1
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%4:gpr(s64) = G_LOAD %2(p0) :: (load 8 from %ir.addr)
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$x0 = COPY %4(s64)
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RET_ReallyLR implicit $x0
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...
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---
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name: ldrdrox_breg_oreg
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0, $x1
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; CHECK-LABEL: name: ldrdrox_breg_oreg
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; CHECK: liveins: $d0, $x1
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $d0
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; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
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; CHECK: [[LDRDroX:%[0-9]+]]:fpr64 = LDRDroX [[COPY]], [[COPY1]], 0, 0 :: (load 8 from %ir.addr)
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; CHECK: $d0 = COPY [[LDRDroX]]
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; CHECK: RET_ReallyLR implicit $d0
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%0:gpr(p0) = COPY $d0
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%1:gpr(s64) = COPY $x1
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%2:gpr(p0) = G_GEP %0, %1
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%4:fpr(s64) = G_LOAD %2(p0) :: (load 8 from %ir.addr)
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$d0 = COPY %4(s64)
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RET_ReallyLR implicit $d0
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...
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---
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name: more_than_one_use
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $x0, $x1
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; This shouldn't be folded, since we reuse the result of the G_GEP outside
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; the G_LOAD
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; CHECK-LABEL: name: more_than_one_use
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; CHECK: liveins: $x0, $x1
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
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; CHECK: [[ADDXrr:%[0-9]+]]:gpr64common = ADDXrr [[COPY]], [[COPY1]]
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; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[ADDXrr]], 0 :: (load 8 from %ir.addr)
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; CHECK: [[COPY2:%[0-9]+]]:gpr64 = COPY [[ADDXrr]]
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; CHECK: [[ADDXrr1:%[0-9]+]]:gpr64 = ADDXrr [[COPY2]], [[LDRXui]]
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; CHECK: $x0 = COPY [[ADDXrr1]]
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; CHECK: RET_ReallyLR implicit $x0
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%0:gpr(p0) = COPY $x0
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%1:gpr(s64) = COPY $x1
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%2:gpr(p0) = G_GEP %0, %1
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%4:gpr(s64) = G_LOAD %2(p0) :: (load 8 from %ir.addr)
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%5:gpr(s64) = G_PTRTOINT %2
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%6:gpr(s64) = G_ADD %5, %4
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$x0 = COPY %6(s64)
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RET_ReallyLR implicit $x0
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