forked from OSchip/llvm-project
[X86][SchedModel] Add missing ReadAdvance for some arithmetic ops (PR51318 and PR51322).
This fixes a bug where implicit uses of EFLAGS were not marked as ReadAdvance in the RM/MR variants of ADC/SBB (PR51318) This also fixes the absence of ReadAdvance for the register operand of RMW arithmetic instructions (PR51322). Differential Revision: https://reviews.llvm.org/D107367
This commit is contained in:
Andrea Di Biagio
parent
680c71b127
commit
7a1a35a1d1
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@ -708,6 +708,19 @@ class BinOpRM<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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mnemonic, "{$src2, $src1|$src1, $src2}", pattern>,
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Sched<[sched.Folded, sched.ReadAfterFold]>;
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// BinOpRM - Instructions like "adc reg, reg, [mem]".
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// There is an implicit register read at the end of the operand sequence.
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class BinOpRM_ImplicitUse<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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dag outlist, X86FoldableSchedWrite sched, list<dag> pattern>
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: ITy<opcode, MRMSrcMem, typeinfo, outlist,
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(ins typeinfo.RegClass:$src1, typeinfo.MemOperand:$src2),
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mnemonic, "{$src2, $src1|$src1, $src2}", pattern>,
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Sched<[sched.Folded, sched.ReadAfterFold,
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// base, scale, index, offset, segment.
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ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault,
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// implicit register read.
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sched.ReadAfterFold]>;
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// BinOpRM_F - Instructions like "cmp reg, [mem]".
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class BinOpRM_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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SDNode opnode>
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@ -725,7 +738,7 @@ class BinOpRM_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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// BinOpRM_RFF - Instructions like "adc reg, reg, [mem]".
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class BinOpRM_RFF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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SDNode opnode>
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: BinOpRM<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst), WriteADC,
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: BinOpRM_ImplicitUse<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst), WriteADC,
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[(set typeinfo.RegClass:$dst, EFLAGS,
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(opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2),
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EFLAGS))]>;
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@ -805,7 +818,11 @@ class BinOpMR_RMW<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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SDNode opnode>
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: BinOpMR<opcode, mnemonic, typeinfo,
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[(store (opnode (load addr:$dst), typeinfo.RegClass:$src), addr:$dst),
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(implicit EFLAGS)]>, Sched<[WriteALURMW]>;
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(implicit EFLAGS)]>, Sched<[WriteALURMW,
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// base, scale, index, offset, segment
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ReadDefault, ReadDefault, ReadDefault,
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ReadDefault, ReadDefault,
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WriteALU.ReadAfterFold]>; // reg
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// BinOpMR_RMW_FF - Instructions like "adc [mem], reg".
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class BinOpMR_RMW_FF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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@ -813,7 +830,12 @@ class BinOpMR_RMW_FF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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: BinOpMR<opcode, mnemonic, typeinfo,
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[(store (opnode (load addr:$dst), typeinfo.RegClass:$src, EFLAGS),
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addr:$dst),
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(implicit EFLAGS)]>, Sched<[WriteADCRMW]>;
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(implicit EFLAGS)]>, Sched<[WriteADCRMW,
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// base, scale, index, offset, segment
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ReadDefault, ReadDefault, ReadDefault,
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ReadDefault, ReadDefault,
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WriteALU.ReadAfterFold, // reg
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WriteALU.ReadAfterFold]>; // EFLAGS
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// BinOpMR_F - Instructions like "cmp [mem], reg".
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class BinOpMR_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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@ -1,19 +1,16 @@
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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=4 -timeline < %s | FileCheck %s
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# FIXME: PR51318
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# Missing read-advance for the implicit use of register EFLAGS.
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adc 4(%rsp), %eax
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# CHECK: Iterations: 4
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# CHECK-NEXT: Instructions: 4
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# CHECK-NEXT: Total Cycles: 19
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# CHECK-NEXT: Total Cycles: 10
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# CHECK-NEXT: Total uOps: 4
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# CHECK: Dispatch Width: 2
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# CHECK-NEXT: uOps Per Cycle: 0.21
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# CHECK-NEXT: IPC: 0.21
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# CHECK-NEXT: uOps Per Cycle: 0.40
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# CHECK-NEXT: IPC: 0.40
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# CHECK-NEXT: Block RThroughput: 1.0
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# CHECK: Instruction Info:
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@ -52,13 +49,12 @@ adc 4(%rsp), %eax
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# CHECK-NEXT: 1.00 1.00 - - - - - 1.00 - - - - - - adcl 4(%rsp), %eax
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# CHECK: Timeline view:
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# CHECK-NEXT: 012345678
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# CHECK-NEXT: Index 0123456789
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# CHECK: [0,0] DeeeeER . . . adcl 4(%rsp), %eax
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# CHECK-NEXT: [1,0] D====eeeeER . . adcl 4(%rsp), %eax
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# CHECK-NEXT: [2,0] .D=======eeeeER. . adcl 4(%rsp), %eax
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# CHECK-NEXT: [3,0] .D===========eeeeER adcl 4(%rsp), %eax
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# CHECK: [0,0] DeeeeER . adcl 4(%rsp), %eax
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# CHECK-NEXT: [1,0] D=eeeeER . adcl 4(%rsp), %eax
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# CHECK-NEXT: [2,0] .D=eeeeER. adcl 4(%rsp), %eax
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# CHECK-NEXT: [3,0] .D==eeeeER adcl 4(%rsp), %eax
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# CHECK: Average Wait times (based on the timeline view):
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# CHECK-NEXT: [0]: Executions
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@ -67,4 +63,4 @@ adc 4(%rsp), %eax
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# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
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# CHECK: [0] [1] [2] [3]
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# CHECK-NEXT: 0. 4 6.5 0.3 0.0 adcl 4(%rsp), %eax
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# CHECK-NEXT: 0. 4 2.0 0.3 0.0 adcl 4(%rsp), %eax
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@ -1,20 +1,17 @@
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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1 -timeline < %s | FileCheck %s
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# FIXME: PR51322
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# Missing read-advance for register EAX.
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add %eax, %eax
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adc %eax, 4(%rsp)
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# CHECK: Iterations: 1
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# CHECK-NEXT: Instructions: 2
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# CHECK-NEXT: Total Cycles: 10
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# CHECK-NEXT: Total Cycles: 9
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# CHECK-NEXT: Total uOps: 2
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# CHECK: Dispatch Width: 2
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# CHECK-NEXT: uOps Per Cycle: 0.20
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# CHECK-NEXT: IPC: 0.20
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# CHECK-NEXT: uOps Per Cycle: 0.22
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# CHECK-NEXT: IPC: 0.22
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# CHECK-NEXT: Block RThroughput: 1.5
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# CHECK: Instruction Info:
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@ -55,10 +52,10 @@ adc %eax, 4(%rsp)
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# CHECK-NEXT: 2.00 - - - - - - 1.00 - 1.00 - - - - adcl %eax, 4(%rsp)
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# CHECK: Timeline view:
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# CHECK-NEXT: Index 0123456789
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# CHECK-NEXT: Index 012345678
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# CHECK: [0,0] DeER . . addl %eax, %eax
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# CHECK-NEXT: [0,1] D=eeeeeeER adcl %eax, 4(%rsp)
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# CHECK: [0,0] DeER . . addl %eax, %eax
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# CHECK-NEXT: [0,1] DeeeeeeER adcl %eax, 4(%rsp)
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# CHECK: Average Wait times (based on the timeline view):
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# CHECK-NEXT: [0]: Executions
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@ -68,5 +65,5 @@ adc %eax, 4(%rsp)
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# CHECK: [0] [1] [2] [3]
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# CHECK-NEXT: 0. 1 1.0 1.0 0.0 addl %eax, %eax
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# CHECK-NEXT: 1. 1 2.0 0.0 0.0 adcl %eax, 4(%rsp)
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# CHECK-NEXT: 1 1.5 0.5 0.0 <total>
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# CHECK-NEXT: 1. 1 1.0 0.0 0.0 adcl %eax, 4(%rsp)
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# CHECK-NEXT: 1 1.0 0.5 0.0 <total>
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@ -1,20 +1,17 @@
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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1 -timeline < %s | FileCheck %s
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# FIXME: PR51322
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# Missing read-advance for register EAX.
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add %eax, %eax
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add %eax, 4(%rsp)
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# CHECK: Iterations: 1
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# CHECK-NEXT: Instructions: 2
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# CHECK-NEXT: Total Cycles: 10
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# CHECK-NEXT: Total Cycles: 9
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# CHECK-NEXT: Total uOps: 2
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# CHECK: Dispatch Width: 2
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# CHECK-NEXT: uOps Per Cycle: 0.20
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# CHECK-NEXT: IPC: 0.20
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# CHECK-NEXT: uOps Per Cycle: 0.22
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# CHECK-NEXT: IPC: 0.22
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# CHECK-NEXT: Block RThroughput: 1.0
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# CHECK: Instruction Info:
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@ -55,10 +52,10 @@ add %eax, 4(%rsp)
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# CHECK-NEXT: 1.00 - - - - - - 1.00 - 1.00 - - - - addl %eax, 4(%rsp)
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# CHECK: Timeline view:
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# CHECK-NEXT: Index 0123456789
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# CHECK-NEXT: Index 012345678
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# CHECK: [0,0] DeER . . addl %eax, %eax
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# CHECK-NEXT: [0,1] D=eeeeeeER addl %eax, 4(%rsp)
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# CHECK: [0,0] DeER . . addl %eax, %eax
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# CHECK-NEXT: [0,1] DeeeeeeER addl %eax, 4(%rsp)
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# CHECK: Average Wait times (based on the timeline view):
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# CHECK-NEXT: [0]: Executions
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@ -68,5 +65,5 @@ add %eax, 4(%rsp)
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# CHECK: [0] [1] [2] [3]
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# CHECK-NEXT: 0. 1 1.0 1.0 0.0 addl %eax, %eax
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# CHECK-NEXT: 1. 1 2.0 0.0 0.0 addl %eax, 4(%rsp)
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# CHECK-NEXT: 1 1.5 0.5 0.0 <total>
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# CHECK-NEXT: 1. 1 1.0 0.0 0.0 addl %eax, 4(%rsp)
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# CHECK-NEXT: 1 1.0 0.5 0.0 <total>
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