forked from OSchip/llvm-project
Do type checks before we bother to do everything else.
llvm-svn: 112039
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@ -415,14 +415,19 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg,
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}
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bool ARMFastISel::ARMSelectLoad(const Instruction *I) {
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// Our register and offset with innocuous defaults.
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unsigned Reg = 0;
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int Offset = 0;
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// If we're an alloca we know we have a frame index and can emit the load
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// directly in short order.
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if (ARMLoadAlloca(I))
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return true;
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// Verify we have a legal type before going any further.
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EVT VT;
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if (!isTypeLegal(I->getType(), VT))
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return false;
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// Our register and offset with innocuous defaults.
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unsigned Reg = 0;
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int Offset = 0;
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// See if we can handle this as Reg + Offset
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if (!ARMComputeRegOffset(I->getOperand(0), Reg, Offset))
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@ -445,10 +450,6 @@ bool ARMFastISel::ARMSelectLoad(const Instruction *I) {
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static_cast<const ARMBaseInstrInfo&>(TII));
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}
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EVT VT;
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if (!isTypeLegal(I->getType(), VT))
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return false;
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unsigned ResultReg;
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// TODO: Verify the additions above work, otherwise we'll need to add the
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// offset instead of 0 and do all sorts of operand munging.
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