forked from OSchip/llvm-project
parent
af635240d5
commit
79f43f195c
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@ -130,7 +130,9 @@ private:
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/// Translate an LLVM store instruction into generic IR.
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bool translateStore(const User &U, MachineIRBuilder &MIRBuilder);
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bool translateMemcpy(const CallInst &CI, MachineIRBuilder &MIRBuilder);
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/// Translate an LLVM string intrinsic (memcpy, memset, ...).
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bool translateMemfunc(const CallInst &CI, MachineIRBuilder &MIRBuilder,
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unsigned Intrinsic);
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void getStackGuard(unsigned DstReg, MachineIRBuilder &MIRBuilder);
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@ -468,13 +468,12 @@ bool IRTranslator::translateGetElementPtr(const User &U,
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return true;
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}
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bool IRTranslator::translateMemcpy(const CallInst &CI,
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MachineIRBuilder &MIRBuilder) {
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bool IRTranslator::translateMemfunc(const CallInst &CI,
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MachineIRBuilder &MIRBuilder,
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unsigned ID) {
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LLT SizeTy{*CI.getArgOperand(2)->getType(), *DL};
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if (cast<PointerType>(CI.getArgOperand(0)->getType())->getAddressSpace() !=
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0 ||
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cast<PointerType>(CI.getArgOperand(1)->getType())->getAddressSpace() !=
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0 ||
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Type *DstTy = CI.getArgOperand(0)->getType();
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if (cast<PointerType>(DstTy)->getAddressSpace() != 0 ||
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SizeTy.getSizeInBits() != DL->getPointerSizeInBits(0))
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return false;
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@ -484,9 +483,24 @@ bool IRTranslator::translateMemcpy(const CallInst &CI,
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Args.emplace_back(getOrCreateVReg(*Arg), Arg->getType());
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}
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MachineOperand Callee = MachineOperand::CreateES("memcpy");
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const char *Callee;
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switch (ID) {
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case Intrinsic::memmove:
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case Intrinsic::memcpy: {
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Type *SrcTy = CI.getArgOperand(1)->getType();
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if(cast<PointerType>(SrcTy)->getAddressSpace() != 0)
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return false;
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Callee = ID == Intrinsic::memcpy ? "memcpy" : "memmove";
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break;
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}
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case Intrinsic::memset:
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Callee = "memset";
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break;
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default:
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return false;
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}
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return CLI->lowerCall(MIRBuilder, Callee,
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return CLI->lowerCall(MIRBuilder, MachineOperand::CreateES(Callee),
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CallLowering::ArgInfo(0, CI.getType()), Args);
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}
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@ -607,7 +621,9 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
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case Intrinsic::smul_with_overflow:
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return translateOverflowIntrinsic(CI, TargetOpcode::G_SMULO, MIRBuilder);
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case Intrinsic::memcpy:
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return translateMemcpy(CI, MIRBuilder);
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case Intrinsic::memmove:
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case Intrinsic::memset:
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return translateMemfunc(CI, MIRBuilder, ID);
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case Intrinsic::eh_typeid_for: {
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GlobalValue *GV = ExtractTypeInfo(CI.getArgOperand(0));
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unsigned Reg = getOrCreateVReg(CI);
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@ -1054,6 +1054,34 @@ define void @test_memcpy(i8* %dst, i8* %src, i64 %size) {
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ret void
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}
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declare void @llvm.memmove.p0i8.p0i8.i64(i8*, i8*, i64, i32 %align, i1 %volatile)
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define void @test_memmove(i8* %dst, i8* %src, i64 %size) {
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; CHECK-LABEL: name: test_memmove
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; CHECK: [[DST:%[0-9]+]](p0) = COPY %x0
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; CHECK: [[SRC:%[0-9]+]](p0) = COPY %x1
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; CHECK: [[SIZE:%[0-9]+]](s64) = COPY %x2
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; CHECK: %x0 = COPY [[DST]]
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; CHECK: %x1 = COPY [[SRC]]
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; CHECK: %x2 = COPY [[SIZE]]
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; CHECK: BL $memmove, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %x0, implicit %x1, implicit %x2
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call void @llvm.memmove.p0i8.p0i8.i64(i8* %dst, i8* %src, i64 %size, i32 1, i1 0)
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ret void
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}
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declare void @llvm.memset.p0i8.i64(i8*, i8, i64, i32 %align, i1 %volatile)
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define void @test_memset(i8* %dst, i8 %val, i64 %size) {
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; CHECK-LABEL: name: test_memset
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; CHECK: [[DST:%[0-9]+]](p0) = COPY %x0
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; CHECK: [[SRC:%[0-9]+]](s8) = COPY %w1
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; CHECK: [[SIZE:%[0-9]+]](s64) = COPY %x2
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; CHECK: %x0 = COPY [[DST]]
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; CHECK: %w1 = COPY [[SRC]]
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; CHECK: %x2 = COPY [[SIZE]]
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; CHECK: BL $memset, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %x0, implicit %w1, implicit %x2
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call void @llvm.memset.p0i8.i64(i8* %dst, i8 %val, i64 %size, i32 1, i1 0)
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ret void
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}
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declare i64 @llvm.objectsize.i64(i8*, i1)
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declare i32 @llvm.objectsize.i32(i8*, i1)
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define void @test_objectsize(i8* %addr0, i8* %addr1) {
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