From 79ea85c6afb56534e77adb908e9f553c319f30c0 Mon Sep 17 00:00:00 2001
From: Nicolai Haehnle <nhaehnle@gmail.com>
Date: Tue, 7 May 2019 09:19:09 +0000
Subject: [PATCH] AMDGPU: Verify that SOP2/SOPC instructions have at most one
 immediate operand

Summary:
No test case because I don't know of a way to trigger this, but I
accidentally caused this to fail while working on a different change.

Change-Id: I8015aa447fe27163cc4e4902205a203bd44bf7e3

Reviewers: arsenm, rampitec

Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D61490

llvm-svn: 360123
---
 llvm/lib/Target/AMDGPU/SIInstrInfo.cpp  | 18 ++++++++++++++++++
 llvm/test/CodeGen/AMDGPU/verify-sop.mir | 21 +++++++++++++++++++++
 2 files changed, 39 insertions(+)
 create mode 100644 llvm/test/CodeGen/AMDGPU/verify-sop.mir

diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 8f4a073839d9..1e77d63ba9d6 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -3191,6 +3191,24 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
     }
   }
 
+  if (isSOP2(MI) || isSOPC(MI)) {
+    const MachineOperand &Src0 = MI.getOperand(Src0Idx);
+    const MachineOperand &Src1 = MI.getOperand(Src1Idx);
+    unsigned Immediates = 0;
+
+    if (!Src0.isReg() &&
+        !isInlineConstant(Src0, Desc.OpInfo[Src0Idx].OperandType))
+      Immediates++;
+    if (!Src1.isReg() &&
+        !isInlineConstant(Src1, Desc.OpInfo[Src1Idx].OperandType))
+      Immediates++;
+
+    if (Immediates > 1) {
+      ErrInfo = "SOP2/SOPC instruction requires too many immediate constants";
+      return false;
+    }
+  }
+
   if (isSOPK(MI)) {
     auto Op = getNamedOperand(MI, AMDGPU::OpName::simm16);
     if (Desc.isBranch()) {
diff --git a/llvm/test/CodeGen/AMDGPU/verify-sop.mir b/llvm/test/CodeGen/AMDGPU/verify-sop.mir
new file mode 100644
index 000000000000..53d749f71196
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/verify-sop.mir
@@ -0,0 +1,21 @@
+# RUN: not llc -march=amdgcn -run-pass machineverifier %s -o - 2>&1 | FileCheck %s
+
+# CHECK: *** Bad machine code: SOP2/SOPC instruction requires too many immediate constants
+# CHECK: - instruction: %0:sreg_32_xm0 = S_ADD_I32
+
+# CHECK: *** Bad machine code: SOP2/SOPC instruction requires too many immediate constants
+# CHECK: - instruction: S_CMP_EQ_U32
+
+# CHECK-NOT: Bad machine code
+
+---
+name: sop2_sopc
+tracksRegLiveness: true
+body: |
+  bb.0:
+    %0:sreg_32_xm0 = S_ADD_I32 2011, -113, implicit-def $scc
+    S_CMP_EQ_U32 2011, -113, implicit-def $scc
+
+    %1:sreg_32_xm0 = S_SUB_I32 2011, 10, implicit-def $scc
+    S_CMP_LG_U32 -5, 2011, implicit-def $scc
+...