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[mips] Define "trap" as a pseudo instruction that turns into "break 0, 0". 

llvm-svn: 190224
This commit is contained in:
Akira Hatanaka 2013-09-06 23:52:46 +00:00
parent 215f96c084
commit 79e38cde37
2 changed files with 11 additions and 3 deletions
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4
llvm/lib/Target/Mips/MipsCodeEmitter.cpp
View File

@ -327,6 +327,10 @@ bool MipsCodeEmitter::expandPseudos(MachineBasicBlock::instr_iterator &MI,
BuildMI(MBB, &*MI, MI->getDebugLoc(), II->get(Mips::BEQ)).addReg(Mips::ZERO)
.addReg(Mips::ZERO).addOperand(MI->getOperand(0));
break;
case Mips::TRAP:
BuildMI(MBB, &*MI, MI->getDebugLoc(), II->get(Mips::BREAK)).addImm(0)
.addImm(0);
break;
case Mips::JALRPseudo:
BuildMI(MBB, &*MI, MI->getDebugLoc(), II->get(Mips::JALR), Mips::RA)
.addReg(MI->getOperand(0).getReg());

10
llvm/lib/Target/Mips/MipsInstrInfo.td
View File

@ -783,9 +783,12 @@ class MFC3OP<string asmstr, RegisterOperand RO> :
InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
!strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
let isBarrier = 1, isTerminator = 1, isCodeGenOnly = 1 in
def TRAP : InstSE<(outs), (ins), "break", [(trap)], NoItinerary, FrmOther> {
let Inst = 0x0000000d;
class TrapBase<Instruction RealInst>
: PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
PseudoInstExpansion<(RealInst 0, 0)> {
let isBarrier = 1;
let isTerminator = 1;
let isCodeGenOnly = 1;
}
//===----------------------------------------------------------------------===//
@ -941,6 +944,7 @@ def TNEI : TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>;
def BREAK : BRK_FT<"break">, BRK_FM<0xd>;
def SYSCALL : SYS_FT<"syscall">, SYS_FM<0xc>;
def TRAP : TrapBase<BREAK>;
def ERET : ER_FT<"eret">, ER_FM<0x18>;
def DERET : ER_FT<"deret">, ER_FM<0x1f>;