forked from OSchip/llvm-project
[AArch64][GlobalISel] Add post-legalizer lowering for NEON vector fcmps
This is roughly equivalent to the floating point portion of `AArch64TargetLowering::LowerVSETCC`. Main part that's missing is the v4s16 bit. This also adds helpers equivalent to `EmitVectorComparison`, and `changeVectorFPCCToAArch64CC`. This moves `changeFCMPPredToAArch64CC` out of the selector into AArch64GlobalISelUtils for the sake of code reuse. This is done in post-legalizer lowering with pseudos to simplify selection. The imported patterns end up handling selection for us this way. Differential Revision: https://reviews.llvm.org/D101782
This commit is contained in:
Jessica Paquette
parent
061e071d8c
commit
79be9c59c6
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@ -176,13 +176,20 @@ def bitfield_extract_from_sext_inreg : GICombineRule<
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def form_bitfield_extract : GICombineGroup<[bitfield_extract_from_sext_inreg]>;
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def lower_vector_fcmp : GICombineRule<
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(defs root:$root),
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(match (wip_match_opcode G_FCMP):$root,
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[{ return lowerVectorFCMP(*${root}, MRI, B); }]),
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(apply [{}])>;
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// Post-legalization combines which should happen at all optimization levels.
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// (E.g. ones that facilitate matching for the selector) For example, matching
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// pseudos.
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def AArch64PostLegalizerLoweringHelper
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: GICombinerHelper<"AArch64GenPostLegalizerLoweringHelper",
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[shuffle_vector_lowering, vashr_vlshr_imm,
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icmp_lowering, build_vector_lowering]> {
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icmp_lowering, build_vector_lowering,
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lower_vector_fcmp]> {
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let DisableRuleOption = "aarch64postlegalizerlowering-disable-rule";
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}
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@ -156,6 +156,54 @@ def G_UITOF : AArch64GenericInstruction {
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let InOperandList = (ins type0:$src);
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}
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def G_FCMEQ : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$src1, type1:$src2);
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let hasSideEffects = 0;
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}
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def G_FCMGE : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$src1, type1:$src2);
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let hasSideEffects = 0;
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}
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def G_FCMGT : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$src1, type1:$src2);
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let hasSideEffects = 0;
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}
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def G_FCMEQZ : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$src);
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let hasSideEffects = 0;
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}
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def G_FCMGEZ : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$src);
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let hasSideEffects = 0;
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}
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def G_FCMGTZ : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$src);
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let hasSideEffects = 0;
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}
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def G_FCMLEZ : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$src);
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let hasSideEffects = 0;
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}
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def G_FCMLTZ : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$src);
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let hasSideEffects = 0;
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}
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def : GINodeEquiv<G_REV16, AArch64rev16>;
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def : GINodeEquiv<G_REV32, AArch64rev32>;
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def : GINodeEquiv<G_REV64, AArch64rev64>;
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@ -176,6 +224,16 @@ def : GINodeEquiv<G_VLSHR, AArch64vlshr>;
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def : GINodeEquiv<G_SITOF, AArch64sitof>;
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def : GINodeEquiv<G_UITOF, AArch64uitof>;
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def : GINodeEquiv<G_FCMEQ, AArch64fcmeq>;
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def : GINodeEquiv<G_FCMGE, AArch64fcmge>;
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def : GINodeEquiv<G_FCMGT, AArch64fcmgt>;
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def : GINodeEquiv<G_FCMEQZ, AArch64fcmeqz>;
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def : GINodeEquiv<G_FCMGEZ, AArch64fcmgez>;
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def : GINodeEquiv<G_FCMGTZ, AArch64fcmgtz>;
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def : GINodeEquiv<G_FCMLEZ, AArch64fcmlez>;
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def : GINodeEquiv<G_FCMLTZ, AArch64fcmltz>;
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def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, vector_extract>;
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// These are patterns that we only use for GlobalISel via the importer.
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@ -12,6 +12,7 @@
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#include "AArch64InstrInfo.h"
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#include "llvm/CodeGen/GlobalISel/Utils.h"
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#include "llvm/CodeGen/TargetLowering.h"
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#include "llvm/IR/InstrTypes.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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@ -93,3 +94,87 @@ bool AArch64GISelUtils::tryEmitBZero(MachineInstr &MI,
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MI.eraseFromParent();
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return true;
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}
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void AArch64GISelUtils::changeFCMPPredToAArch64CC(
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const CmpInst::Predicate P, AArch64CC::CondCode &CondCode,
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AArch64CC::CondCode &CondCode2) {
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CondCode2 = AArch64CC::AL;
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switch (P) {
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default:
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llvm_unreachable("Unknown FP condition!");
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case CmpInst::FCMP_OEQ:
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CondCode = AArch64CC::EQ;
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break;
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case CmpInst::FCMP_OGT:
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CondCode = AArch64CC::GT;
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break;
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case CmpInst::FCMP_OGE:
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CondCode = AArch64CC::GE;
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break;
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case CmpInst::FCMP_OLT:
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CondCode = AArch64CC::MI;
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break;
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case CmpInst::FCMP_OLE:
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CondCode = AArch64CC::LS;
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break;
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case CmpInst::FCMP_ONE:
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CondCode = AArch64CC::MI;
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CondCode2 = AArch64CC::GT;
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break;
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case CmpInst::FCMP_ORD:
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CondCode = AArch64CC::VC;
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break;
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case CmpInst::FCMP_UNO:
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CondCode = AArch64CC::VS;
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break;
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case CmpInst::FCMP_UEQ:
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CondCode = AArch64CC::EQ;
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CondCode2 = AArch64CC::VS;
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break;
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case CmpInst::FCMP_UGT:
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CondCode = AArch64CC::HI;
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break;
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case CmpInst::FCMP_UGE:
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CondCode = AArch64CC::PL;
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break;
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case CmpInst::FCMP_ULT:
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CondCode = AArch64CC::LT;
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break;
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case CmpInst::FCMP_ULE:
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CondCode = AArch64CC::LE;
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break;
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case CmpInst::FCMP_UNE:
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CondCode = AArch64CC::NE;
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break;
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}
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}
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void AArch64GISelUtils::changeVectorFCMPPredToAArch64CC(
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const CmpInst::Predicate P, AArch64CC::CondCode &CondCode,
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AArch64CC::CondCode &CondCode2, bool &Invert) {
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Invert = false;
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switch (P) {
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default:
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// Mostly the scalar mappings work fine.
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changeFCMPPredToAArch64CC(P, CondCode, CondCode2);
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break;
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case CmpInst::FCMP_UNO:
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Invert = true;
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LLVM_FALLTHROUGH;
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case CmpInst::FCMP_ORD:
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CondCode = AArch64CC::MI;
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CondCode2 = AArch64CC::GE;
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break;
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case CmpInst::FCMP_UEQ:
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case CmpInst::FCMP_ULT:
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case CmpInst::FCMP_ULE:
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case CmpInst::FCMP_UGT:
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case CmpInst::FCMP_UGE:
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// All of the compare-mask comparisons are ordered, but we can switch
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// between the two by a double inversion. E.g. ULE == !OGT.
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Invert = true;
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changeFCMPPredToAArch64CC(CmpInst::getInversePredicate(P), CondCode,
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CondCode2);
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break;
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}
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}
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@ -11,12 +11,12 @@
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#ifndef LLVM_LIB_TARGET_AARCH64_GISEL_AARCH64GLOBALISELUTILS_H
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#define LLVM_LIB_TARGET_AARCH64_GISEL_AARCH64GLOBALISELUTILS_H
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#include "MCTargetDesc/AArch64AddressingModes.h"
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#include "Utils/AArch64BaseInfo.h"
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#include "llvm/ADT/Optional.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/GlobalISel/Utils.h"
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#include "llvm/CodeGen/Register.h"
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#include "MCTargetDesc/AArch64AddressingModes.h"
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#include "llvm/IR/InstrTypes.h"
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#include <cstdint>
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@ -53,6 +53,28 @@ bool isCMN(const MachineInstr *MaybeSub, const CmpInst::Predicate &Pred,
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/// \returns true if \p MI was replaced with a G_BZERO.
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bool tryEmitBZero(MachineInstr &MI, MachineIRBuilder &MIRBuilder, bool MinSize);
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/// Find the AArch64 condition codes necessary to represent \p P for a scalar
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/// floating point comparison.
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///
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/// \param [out] CondCode is the first condition code.
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/// \param [out] CondCode2 is the second condition code if necessary.
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/// AArch64CC::AL otherwise.
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void changeFCMPPredToAArch64CC(const CmpInst::Predicate P,
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AArch64CC::CondCode &CondCode,
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AArch64CC::CondCode &CondCode2);
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/// Find the AArch64 condition codes necessary to represent \p P for a vector
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/// floating point comparison.
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///
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/// \param [out] CondCode - The first condition code.
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/// \param [out] CondCode2 - The second condition code if necessary.
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/// AArch64CC::AL otherwise.
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/// \param [out] Invert - True if the comparison must be inverted with a NOT.
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void changeVectorFCMPPredToAArch64CC(const CmpInst::Predicate P,
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AArch64CC::CondCode &CondCode,
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AArch64CC::CondCode &CondCode2,
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bool &Invert);
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} // namespace AArch64GISelUtils
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} // namespace llvm
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@ -1231,60 +1231,6 @@ static AArch64CC::CondCode changeICMPPredToAArch64CC(CmpInst::Predicate P) {
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}
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}
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static void changeFCMPPredToAArch64CC(CmpInst::Predicate P,
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AArch64CC::CondCode &CondCode,
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AArch64CC::CondCode &CondCode2) {
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CondCode2 = AArch64CC::AL;
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switch (P) {
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default:
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llvm_unreachable("Unknown FP condition!");
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case CmpInst::FCMP_OEQ:
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CondCode = AArch64CC::EQ;
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break;
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case CmpInst::FCMP_OGT:
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CondCode = AArch64CC::GT;
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break;
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case CmpInst::FCMP_OGE:
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CondCode = AArch64CC::GE;
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break;
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case CmpInst::FCMP_OLT:
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CondCode = AArch64CC::MI;
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break;
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case CmpInst::FCMP_OLE:
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CondCode = AArch64CC::LS;
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break;
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case CmpInst::FCMP_ONE:
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CondCode = AArch64CC::MI;
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CondCode2 = AArch64CC::GT;
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break;
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case CmpInst::FCMP_ORD:
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CondCode = AArch64CC::VC;
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break;
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case CmpInst::FCMP_UNO:
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CondCode = AArch64CC::VS;
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break;
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case CmpInst::FCMP_UEQ:
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CondCode = AArch64CC::EQ;
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CondCode2 = AArch64CC::VS;
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break;
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case CmpInst::FCMP_UGT:
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CondCode = AArch64CC::HI;
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break;
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case CmpInst::FCMP_UGE:
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CondCode = AArch64CC::PL;
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break;
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case CmpInst::FCMP_ULT:
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CondCode = AArch64CC::LT;
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break;
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case CmpInst::FCMP_ULE:
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CondCode = AArch64CC::LE;
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break;
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case CmpInst::FCMP_UNE:
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CondCode = AArch64CC::NE;
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break;
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}
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}
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/// Return a register which can be used as a bit to test in a TB(N)Z.
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static Register getTestBitReg(Register Reg, uint64_t &Bit, bool &Invert,
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MachineRegisterInfo &MRI) {
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@ -19,9 +19,13 @@
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///
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//===----------------------------------------------------------------------===//
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#include "AArch64TargetMachine.h"
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#include "AArch64GlobalISelUtils.h"
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#include "AArch64Subtarget.h"
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#include "AArch64TargetMachine.h"
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#include "GISel/AArch64LegalizerInfo.h"
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#include "MCTargetDesc/AArch64MCTargetDesc.h"
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#include "TargetInfo/AArch64TargetInfo.h"
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#include "Utils/AArch64BaseInfo.h"
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#include "llvm/CodeGen/GlobalISel/Combiner.h"
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#include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
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#include "llvm/CodeGen/GlobalISel/CombinerInfo.h"
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@ -33,8 +37,10 @@
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetOpcodes.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/IR/InstrTypes.h"
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#include "llvm/InitializePasses.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#define DEBUG_TYPE "aarch64-postlegalizer-lowering"
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@ -842,6 +848,109 @@ static bool applySwapICmpOperands(MachineInstr &MI,
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return true;
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}
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/// \returns a function which builds a vector floating point compare instruction
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/// for a condition code \p CC.
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/// \param [in] IsZero - True if the comparison is against 0.
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/// \param [in] NoNans - True if the target has NoNansFPMath.
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static std::function<Register(MachineIRBuilder &)>
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getVectorFCMP(AArch64CC::CondCode CC, Register LHS, Register RHS, bool IsZero,
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bool NoNans, MachineRegisterInfo &MRI) {
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LLT DstTy = MRI.getType(LHS);
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assert(DstTy.isVector() && "Expected vector types only?");
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assert(DstTy == MRI.getType(RHS) && "Src and Dst types must match!");
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switch (CC) {
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default:
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llvm_unreachable("Unexpected condition code!");
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case AArch64CC::NE:
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return [LHS, RHS, IsZero, DstTy](MachineIRBuilder &MIB) {
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auto FCmp = IsZero
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? MIB.buildInstr(AArch64::G_FCMEQZ, {DstTy}, {LHS})
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: MIB.buildInstr(AArch64::G_FCMEQ, {DstTy}, {LHS, RHS});
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return MIB.buildNot(DstTy, FCmp).getReg(0);
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};
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case AArch64CC::EQ:
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return [LHS, RHS, IsZero, DstTy](MachineIRBuilder &MIB) {
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return IsZero
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? MIB.buildInstr(AArch64::G_FCMEQZ, {DstTy}, {LHS}).getReg(0)
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: MIB.buildInstr(AArch64::G_FCMEQ, {DstTy}, {LHS, RHS})
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.getReg(0);
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};
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case AArch64CC::GE:
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return [LHS, RHS, IsZero, DstTy](MachineIRBuilder &MIB) {
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return IsZero
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? MIB.buildInstr(AArch64::G_FCMGEZ, {DstTy}, {LHS}).getReg(0)
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: MIB.buildInstr(AArch64::G_FCMGE, {DstTy}, {LHS, RHS})
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.getReg(0);
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};
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case AArch64CC::GT:
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return [LHS, RHS, IsZero, DstTy](MachineIRBuilder &MIB) {
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return IsZero
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? MIB.buildInstr(AArch64::G_FCMGTZ, {DstTy}, {LHS}).getReg(0)
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: MIB.buildInstr(AArch64::G_FCMGT, {DstTy}, {LHS, RHS})
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.getReg(0);
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};
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case AArch64CC::LS:
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return [LHS, RHS, IsZero, DstTy](MachineIRBuilder &MIB) {
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return IsZero
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? MIB.buildInstr(AArch64::G_FCMLEZ, {DstTy}, {LHS}).getReg(0)
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: MIB.buildInstr(AArch64::G_FCMGE, {DstTy}, {RHS, LHS})
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.getReg(0);
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};
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case AArch64CC::MI:
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return [LHS, RHS, IsZero, DstTy](MachineIRBuilder &MIB) {
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return IsZero
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? MIB.buildInstr(AArch64::G_FCMLTZ, {DstTy}, {LHS}).getReg(0)
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: MIB.buildInstr(AArch64::G_FCMGT, {DstTy}, {RHS, LHS})
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.getReg(0);
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};
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}
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}
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/// Try to lower a vector G_FCMP \p MI into an AArch64-specific pseudo.
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static bool lowerVectorFCMP(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &MIB) {
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assert(MI.getOpcode() == TargetOpcode::G_FCMP);
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const auto &ST = MI.getMF()->getSubtarget<AArch64Subtarget>();
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Register Dst = MI.getOperand(0).getReg();
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LLT DstTy = MRI.getType(Dst);
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if (!DstTy.isVector() || !ST.hasNEON())
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return false;
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const auto Pred =
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static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
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Register LHS = MI.getOperand(2).getReg();
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// TODO: Handle v4s16 case.
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unsigned EltSize = MRI.getType(LHS).getScalarSizeInBits();
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if (EltSize != 32 && EltSize != 64)
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return false;
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||||
Register RHS = MI.getOperand(3).getReg();
|
||||
auto Splat = getAArch64VectorSplat(*MRI.getVRegDef(RHS), MRI);
|
||||
|
||||
// Compares against 0 have special target-specific pseudos.
|
||||
bool IsZero = Splat && Splat->isCst() && Splat->getCst() == 0;
|
||||
bool Invert;
|
||||
AArch64CC::CondCode CC, CC2;
|
||||
changeVectorFCMPPredToAArch64CC(Pred, CC, CC2, Invert);
|
||||
bool NoNans = ST.getTargetLowering()->getTargetMachine().Options.NoNaNsFPMath;
|
||||
|
||||
// Instead of having an apply function, just build here to simplify things.
|
||||
MIB.setInstrAndDebugLoc(MI);
|
||||
auto Cmp = getVectorFCMP(CC, LHS, RHS, IsZero, NoNans, MRI);
|
||||
Register CmpRes;
|
||||
if (CC2 == AArch64CC::AL)
|
||||
CmpRes = Cmp(MIB);
|
||||
else {
|
||||
auto Cmp2 = getVectorFCMP(CC2, LHS, RHS, IsZero, NoNans, MRI);
|
||||
auto Cmp2Dst = Cmp2(MIB);
|
||||
auto Cmp1Dst = Cmp(MIB);
|
||||
CmpRes = MIB.buildOr(DstTy, Cmp1Dst, Cmp2Dst).getReg(0);
|
||||
}
|
||||
if (Invert)
|
||||
CmpRes = MIB.buildNot(DstTy, CmpRes).getReg(0);
|
||||
MRI.replaceRegWith(Dst, CmpRes);
|
||||
MI.eraseFromParent();
|
||||
return false;
|
||||
}
|
||||
|
||||
#define AARCH64POSTLEGALIZERLOWERINGHELPER_GENCOMBINERHELPER_DEPS
|
||||
#include "AArch64GenPostLegalizeGILowering.inc"
|
||||
#undef AARCH64POSTLEGALIZERLOWERINGHELPER_GENCOMBINERHELPER_DEPS
|
||||
|
|
|
|||
|
|
@ -0,0 +1,672 @@
|
|||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple aarch64 -run-pass=aarch64-postlegalizer-lowering -verify-machineinstrs %s -o - | FileCheck %s
|
||||
...
|
||||
---
|
||||
name: oeq
|
||||
alignment: 4
|
||||
legalized: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $q0, $q1
|
||||
; CHECK-LABEL: name: oeq
|
||||
; CHECK: %lhs:_(<2 x s64>) = COPY $q0
|
||||
; CHECK: %rhs:_(<2 x s64>) = COPY $q1
|
||||
; CHECK: [[FCMEQ:%[0-9]+]]:_(<2 x s64>) = G_FCMEQ %lhs, %rhs(<2 x s64>)
|
||||
; CHECK: $q0 = COPY [[FCMEQ]](<2 x s64>)
|
||||
; CHECK: RET_ReallyLR implicit $q0
|
||||
%lhs:_(<2 x s64>) = COPY $q0
|
||||
%rhs:_(<2 x s64>) = COPY $q1
|
||||
%fcmp:_(<2 x s64>) = G_FCMP floatpred(oeq), %lhs(<2 x s64>), %rhs
|
||||
$q0 = COPY %fcmp(<2 x s64>)
|
||||
RET_ReallyLR implicit $q0
|
||||
|
||||
...
|
||||
---
|
||||
name: oeq_zero
|
||||
alignment: 4
|
||||
legalized: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $q0, $q1
|
||||
|
||||
; Should be inverted. Needs two compares.
|
||||
|
||||
; CHECK-LABEL: name: oeq_zero
|
||||
; CHECK: %lhs:_(<2 x s64>) = COPY $q0
|
||||
; CHECK: %zero:_(s64) = G_CONSTANT i64 0
|
||||
; CHECK: %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
|
||||
; CHECK: [[FCMEQZ:%[0-9]+]]:_(<2 x s64>) = G_FCMEQZ %lhs
|
||||
; CHECK: $q0 = COPY [[FCMEQZ]](<2 x s64>)
|
||||
; CHECK: RET_ReallyLR implicit $q0
|
||||
%lhs:_(<2 x s64>) = COPY $q0
|
||||
%zero:_(s64) = G_CONSTANT i64 0
|
||||
%zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero, %zero
|
||||
%fcmp:_(<2 x s64>) = G_FCMP floatpred(oeq), %lhs(<2 x s64>), %zero_vec
|
||||
$q0 = COPY %fcmp(<2 x s64>)
|
||||
RET_ReallyLR implicit $q0
|
||||
|
||||
|
||||
...
|
||||
---
|
||||
name: ogt
|
||||
alignment: 4
|
||||
legalized: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $q0, $q1
|
||||
; CHECK-LABEL: name: ogt
|
||||
; CHECK: %lhs:_(<2 x s64>) = COPY $q0
|
||||
; CHECK: %rhs:_(<2 x s64>) = COPY $q1
|
||||
; CHECK: [[FCMGT:%[0-9]+]]:_(<2 x s64>) = G_FCMGT %lhs, %rhs(<2 x s64>)
|
||||
; CHECK: $q0 = COPY [[FCMGT]](<2 x s64>)
|
||||
; CHECK: RET_ReallyLR implicit $q0
|
||||
%lhs:_(<2 x s64>) = COPY $q0
|
||||
%rhs:_(<2 x s64>) = COPY $q1
|
||||
%fcmp:_(<2 x s64>) = G_FCMP floatpred(ogt), %lhs(<2 x s64>), %rhs
|
||||
$q0 = COPY %fcmp(<2 x s64>)
|
||||
RET_ReallyLR implicit $q0
|
||||
|
||||
...
|
||||
---
|
||||
name: ogt_zero
|
||||
alignment: 4
|
||||
legalized: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $q0, $q1
|
||||
; CHECK-LABEL: name: ogt_zero
|
||||
; CHECK: %lhs:_(<2 x s64>) = COPY $q0
|
||||
; CHECK: %zero:_(s64) = G_CONSTANT i64 0
|
||||
; CHECK: %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
|
||||
; CHECK: [[FCMGTZ:%[0-9]+]]:_(<2 x s64>) = G_FCMGTZ %lhs
|
||||
; CHECK: $q0 = COPY [[FCMGTZ]](<2 x s64>)
|
||||
; CHECK: RET_ReallyLR implicit $q0
|
||||
%lhs:_(<2 x s64>) = COPY $q0
|
||||
%zero:_(s64) = G_CONSTANT i64 0
|
||||
%zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero, %zero
|
||||
%fcmp:_(<2 x s64>) = G_FCMP floatpred(ogt), %lhs(<2 x s64>), %zero_vec
|
||||
$q0 = COPY %fcmp(<2 x s64>)
|
||||
RET_ReallyLR implicit $q0
|
||||
|
||||
...
|
||||
---
|
||||
name: oge
|
||||
alignment: 4
|
||||
legalized: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $q0, $q1
|
||||
; CHECK-LABEL: name: oge
|
||||
; CHECK: %lhs:_(<2 x s64>) = COPY $q0
|
||||
; CHECK: %rhs:_(<2 x s64>) = COPY $q1
|
||||
; CHECK: [[FCMGE:%[0-9]+]]:_(<2 x s64>) = G_FCMGE %lhs, %rhs(<2 x s64>)
|
||||
; CHECK: $q0 = COPY [[FCMGE]](<2 x s64>)
|
||||
; CHECK: RET_ReallyLR implicit $q0
|
||||
%lhs:_(<2 x s64>) = COPY $q0
|
||||
%rhs:_(<2 x s64>) = COPY $q1
|
||||
%fcmp:_(<2 x s64>) = G_FCMP floatpred(oge), %lhs(<2 x s64>), %rhs
|
||||
$q0 = COPY %fcmp(<2 x s64>)
|
||||
RET_ReallyLR implicit $q0
|
||||
|
||||
...
|
||||
---
|
||||
name: oge_zero
|
||||
alignment: 4
|
||||
legalized: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $q0, $q1
|
||||
|
||||
; Should be inverted. Needs two compares.
|
||||
|
||||
; CHECK-LABEL: name: oge_zero
|
||||
; CHECK: %lhs:_(<2 x s64>) = COPY $q0
|
||||
; CHECK: %zero:_(s64) = G_CONSTANT i64 0
|
||||
; CHECK: %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
|
||||
; CHECK: [[FCMGEZ:%[0-9]+]]:_(<2 x s64>) = G_FCMGEZ %lhs
|
||||
; CHECK: $q0 = COPY [[FCMGEZ]](<2 x s64>)
|
||||
; CHECK: RET_ReallyLR implicit $q0
|
||||
%lhs:_(<2 x s64>) = COPY $q0
|
||||
%zero:_(s64) = G_CONSTANT i64 0
|
||||
%zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero, %zero
|
||||
%fcmp:_(<2 x s64>) = G_FCMP floatpred(oge), %lhs(<2 x s64>), %zero_vec
|
||||
$q0 = COPY %fcmp(<2 x s64>)
|
||||
RET_ReallyLR implicit $q0
|
||||
|
||||
|
||||
...
|
||||
---
|
||||
name: olt
|
||||
alignment: 4
|
||||
legalized: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $q0, $q1
|
||||
; CHECK-LABEL: name: olt
|
||||
; CHECK: %lhs:_(<2 x s64>) = COPY $q0
|
||||
; CHECK: %rhs:_(<2 x s64>) = COPY $q1
|
||||
; CHECK: [[FCMGT:%[0-9]+]]:_(<2 x s64>) = G_FCMGT %rhs, %lhs(<2 x s64>)
|
||||
; CHECK: $q0 = COPY [[FCMGT]](<2 x s64>)
|
||||
; CHECK: RET_ReallyLR implicit $q0
|
||||
%lhs:_(<2 x s64>) = COPY $q0
|
||||
%rhs:_(<2 x s64>) = COPY $q1
|
||||
%fcmp:_(<2 x s64>) = G_FCMP floatpred(olt), %lhs(<2 x s64>), %rhs
|
||||
$q0 = COPY %fcmp(<2 x s64>)
|
||||
RET_ReallyLR implicit $q0
|
||||
|
||||
...
|
||||
---
|
||||
name: olt_zero
|
||||
alignment: 4
|
||||
legalized: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $q0, $q1
|
||||
; CHECK-LABEL: name: olt_zero
|
||||
; CHECK: %lhs:_(<2 x s64>) = COPY $q0
|
||||
; CHECK: %zero:_(s64) = G_CONSTANT i64 0
|
||||
; CHECK: %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
|
||||
; CHECK: [[FCMLTZ:%[0-9]+]]:_(<2 x s64>) = G_FCMLTZ %lhs
|
||||
; CHECK: $q0 = COPY [[FCMLTZ]](<2 x s64>)
|
||||
; CHECK: RET_ReallyLR implicit $q0
|
||||
%lhs:_(<2 x s64>) = COPY $q0
|
||||
%zero:_(s64) = G_CONSTANT i64 0
|
||||
%zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero, %zero
|
||||
%fcmp:_(<2 x s64>) = G_FCMP floatpred(olt), %lhs(<2 x s64>), %zero_vec
|
||||
$q0 = COPY %fcmp(<2 x s64>)
|
||||
RET_ReallyLR implicit $q0
|
||||
|
||||
...
|
||||
---
|
||||
name: ole
|
||||
alignment: 4
|
||||
legalized: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $q0, $q1
|
||||
; CHECK-LABEL: name: ole
|
||||
; CHECK: %lhs:_(<2 x s64>) = COPY $q0
|
||||
; CHECK: %rhs:_(<2 x s64>) = COPY $q1
|
||||
; CHECK: [[FCMGE:%[0-9]+]]:_(<2 x s64>) = G_FCMGE %rhs, %lhs(<2 x s64>)
|
||||
; CHECK: $q0 = COPY [[FCMGE]](<2 x s64>)
|
||||
; CHECK: RET_ReallyLR implicit $q0
|
||||
%lhs:_(<2 x s64>) = COPY $q0
|
||||
%rhs:_(<2 x s64>) = COPY $q1
|
||||
%fcmp:_(<2 x s64>) = G_FCMP floatpred(ole), %lhs(<2 x s64>), %rhs
|
||||
$q0 = COPY %fcmp(<2 x s64>)
|
||||
RET_ReallyLR implicit $q0
|
||||
|
||||
...
|
||||
---
|
||||
name: ole_zero
|
||||
alignment: 4
|
||||
legalized: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $q0, $q1
|
||||
; CHECK-LABEL: name: ole_zero
|
||||
; CHECK: %lhs:_(<2 x s64>) = COPY $q0
|
||||
; CHECK: %zero:_(s64) = G_CONSTANT i64 0
|
||||
; CHECK: %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
|
||||
; CHECK: [[FCMLEZ:%[0-9]+]]:_(<2 x s64>) = G_FCMLEZ %lhs
|
||||
; CHECK: $q0 = COPY [[FCMLEZ]](<2 x s64>)
|
||||
; CHECK: RET_ReallyLR implicit $q0
|
||||
%lhs:_(<2 x s64>) = COPY $q0
|
||||
%zero:_(s64) = G_CONSTANT i64 0
|
||||
%zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero, %zero
|
||||
%fcmp:_(<2 x s64>) = G_FCMP floatpred(ole), %lhs(<2 x s64>), %zero_vec
|
||||
$q0 = COPY %fcmp(<2 x s64>)
|
||||
RET_ReallyLR implicit $q0
|
||||
|
||||
...
|
||||
---
|
||||
name: one
|
||||
alignment: 4
|
||||
legalized: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $q0, $q1
|
||||
|
||||
; Two compares.
|
||||
|
||||
; CHECK-LABEL: name: one
|
||||
; CHECK: %lhs:_(<2 x s64>) = COPY $q0
|
||||
; CHECK: %rhs:_(<2 x s64>) = COPY $q1
|
||||
; CHECK: [[FCMGT:%[0-9]+]]:_(<2 x s64>) = G_FCMGT %lhs, %rhs(<2 x s64>)
|
||||
; CHECK: [[FCMGT1:%[0-9]+]]:_(<2 x s64>) = G_FCMGT %rhs, %lhs(<2 x s64>)
|
||||
; CHECK: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[FCMGT1]], [[FCMGT]]
|
||||
; CHECK: $q0 = COPY [[OR]](<2 x s64>)
|
||||
; CHECK: RET_ReallyLR implicit $q0
|
||||
%lhs:_(<2 x s64>) = COPY $q0
|
||||
%rhs:_(<2 x s64>) = COPY $q1
|
||||
%fcmp:_(<2 x s64>) = G_FCMP floatpred(one), %lhs(<2 x s64>), %rhs
|
||||
$q0 = COPY %fcmp(<2 x s64>)
|
||||
RET_ReallyLR implicit $q0
|
||||
|
||||
...
|
||||
---
|
||||
name: one_zero
|
||||
alignment: 4
|
||||
legalized: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $q0, $q1
|
||||
|
||||
; Two compares.
|
||||
|
||||
; CHECK-LABEL: name: one_zero
|
||||
; CHECK: %lhs:_(<2 x s64>) = COPY $q0
|
||||
; CHECK: %zero:_(s64) = G_CONSTANT i64 0
|
||||
; CHECK: %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
|
||||
; CHECK: [[FCMGTZ:%[0-9]+]]:_(<2 x s64>) = G_FCMGTZ %lhs
|
||||
; CHECK: [[FCMLTZ:%[0-9]+]]:_(<2 x s64>) = G_FCMLTZ %lhs
|
||||
; CHECK: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[FCMLTZ]], [[FCMGTZ]]
|
||||
; CHECK: $q0 = COPY [[OR]](<2 x s64>)
|
||||
; CHECK: RET_ReallyLR implicit $q0
|
||||
%lhs:_(<2 x s64>) = COPY $q0
|
||||
%zero:_(s64) = G_CONSTANT i64 0
|
||||
%zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero, %zero
|
||||
%fcmp:_(<2 x s64>) = G_FCMP floatpred(one), %lhs(<2 x s64>), %zero_vec
|
||||
$q0 = COPY %fcmp(<2 x s64>)
|
||||
RET_ReallyLR implicit $q0
|
||||
|
||||
...
|
||||
---
|
||||
name: uno
|
||||
alignment: 4
|
||||
legalized: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $q0, $q1
|
||||
|
||||
; Should be inverted. Needs two compares.
|
||||
|
||||
; CHECK-LABEL: name: uno
|
||||
; CHECK: %lhs:_(<2 x s64>) = COPY $q0
|
||||
; CHECK: %rhs:_(<2 x s64>) = COPY $q1
|
||||
; CHECK: [[FCMGE:%[0-9]+]]:_(<2 x s64>) = G_FCMGE %lhs, %rhs(<2 x s64>)
|
||||
; CHECK: [[FCMGT:%[0-9]+]]:_(<2 x s64>) = G_FCMGT %rhs, %lhs(<2 x s64>)
|
||||
; CHECK: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[FCMGT]], [[FCMGE]]
|
||||
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
|
||||
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
|
||||
; CHECK: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[OR]], [[BUILD_VECTOR]]
|
||||
; CHECK: $q0 = COPY [[XOR]](<2 x s64>)
|
||||
; CHECK: RET_ReallyLR implicit $q0
|
||||
%lhs:_(<2 x s64>) = COPY $q0
|
||||
%rhs:_(<2 x s64>) = COPY $q1
|
||||
%fcmp:_(<2 x s64>) = G_FCMP floatpred(uno), %lhs(<2 x s64>), %rhs
|
||||
$q0 = COPY %fcmp(<2 x s64>)
|
||||
RET_ReallyLR implicit $q0
|
||||
|
||||
...
|
||||
---
|
||||
name: uno_zero
|
||||
alignment: 4
|
||||
legalized: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $q0, $q1
|
||||
|
||||
; Should be inverted. Needs two compares.
|
||||
|
||||
; CHECK-LABEL: name: uno_zero
|
||||
; CHECK: %lhs:_(<2 x s64>) = COPY $q0
|
||||
; CHECK: %zero:_(s64) = G_CONSTANT i64 0
|
||||
; CHECK: %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
|
||||
; CHECK: [[FCMGEZ:%[0-9]+]]:_(<2 x s64>) = G_FCMGEZ %lhs
|
||||
; CHECK: [[FCMLTZ:%[0-9]+]]:_(<2 x s64>) = G_FCMLTZ %lhs
|
||||
; CHECK: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[FCMLTZ]], [[FCMGEZ]]
|
||||
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
|
||||
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
|
||||
; CHECK: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[OR]], [[BUILD_VECTOR]]
|
||||
; CHECK: $q0 = COPY [[XOR]](<2 x s64>)
|
||||
; CHECK: RET_ReallyLR implicit $q0
|
||||
%lhs:_(<2 x s64>) = COPY $q0
|
||||
%zero:_(s64) = G_CONSTANT i64 0
|
||||
%zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero, %zero
|
||||
%fcmp:_(<2 x s64>) = G_FCMP floatpred(uno), %lhs(<2 x s64>), %zero_vec
|
||||
$q0 = COPY %fcmp(<2 x s64>)
|
||||
RET_ReallyLR implicit $q0
|
||||
|
||||
...
|
||||
---
|
||||
name: ord
|
||||
alignment: 4
|
||||
legalized: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $q0, $q1
|
||||
|
||||
; Needs two compares. No invert.
|
||||
|
||||
; CHECK-LABEL: name: ord
|
||||
; CHECK: %lhs:_(<2 x s64>) = COPY $q0
|
||||
; CHECK: %rhs:_(<2 x s64>) = COPY $q1
|
||||
; CHECK: [[FCMGE:%[0-9]+]]:_(<2 x s64>) = G_FCMGE %lhs, %rhs(<2 x s64>)
|
||||
; CHECK: [[FCMGT:%[0-9]+]]:_(<2 x s64>) = G_FCMGT %rhs, %lhs(<2 x s64>)
|
||||
; CHECK: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[FCMGT]], [[FCMGE]]
|
||||
; CHECK: $q0 = COPY [[OR]](<2 x s64>)
|
||||
; CHECK: RET_ReallyLR implicit $q0
|
||||
%lhs:_(<2 x s64>) = COPY $q0
|
||||
%rhs:_(<2 x s64>) = COPY $q1
|
||||
%fcmp:_(<2 x s64>) = G_FCMP floatpred(ord), %lhs(<2 x s64>), %rhs
|
||||
$q0 = COPY %fcmp(<2 x s64>)
|
||||
RET_ReallyLR implicit $q0
|
||||
|
||||
...
|
||||
---
|
||||
name: ord_zero
|
||||
alignment: 4
|
||||
legalized: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $q0, $q1
|
||||
|
||||
; Needs two compares. No invert.
|
||||
|
||||
; CHECK-LABEL: name: ord_zero
|
||||
; CHECK: %lhs:_(<2 x s64>) = COPY $q0
|
||||
; CHECK: %zero:_(s64) = G_CONSTANT i64 0
|
||||
; CHECK: %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
|
||||
; CHECK: [[FCMGEZ:%[0-9]+]]:_(<2 x s64>) = G_FCMGEZ %lhs
|
||||
; CHECK: [[FCMLTZ:%[0-9]+]]:_(<2 x s64>) = G_FCMLTZ %lhs
|
||||
; CHECK: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[FCMLTZ]], [[FCMGEZ]]
|
||||
; CHECK: $q0 = COPY [[OR]](<2 x s64>)
|
||||
; CHECK: RET_ReallyLR implicit $q0
|
||||
%lhs:_(<2 x s64>) = COPY $q0
|
||||
%zero:_(s64) = G_CONSTANT i64 0
|
||||
%zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero, %zero
|
||||
%fcmp:_(<2 x s64>) = G_FCMP floatpred(ord), %lhs(<2 x s64>), %zero_vec
|
||||
$q0 = COPY %fcmp(<2 x s64>)
|
||||
RET_ReallyLR implicit $q0
|
||||
|
||||
...
|
||||
---
|
||||
name: ult
|
||||
alignment: 4
|
||||
legalized: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $q0, $q1
|
||||
|
||||
; Should be inverted. Needs two compares.
|
||||
|
||||
; CHECK-LABEL: name: ult
|
||||
; CHECK: %lhs:_(<2 x s64>) = COPY $q0
|
||||
; CHECK: %rhs:_(<2 x s64>) = COPY $q1
|
||||
; CHECK: [[FCMGE:%[0-9]+]]:_(<2 x s64>) = G_FCMGE %lhs, %rhs(<2 x s64>)
|
||||
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
|
||||
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
|
||||
; CHECK: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[FCMGE]], [[BUILD_VECTOR]]
|
||||
; CHECK: $q0 = COPY [[XOR]](<2 x s64>)
|
||||
; CHECK: RET_ReallyLR implicit $q0
|
||||
%lhs:_(<2 x s64>) = COPY $q0
|
||||
%rhs:_(<2 x s64>) = COPY $q1
|
||||
%fcmp:_(<2 x s64>) = G_FCMP floatpred(ult), %lhs(<2 x s64>), %rhs
|
||||
$q0 = COPY %fcmp(<2 x s64>)
|
||||
RET_ReallyLR implicit $q0
|
||||
|
||||
...
|
||||
---
|
||||
name: ueq_zero
|
||||
alignment: 4
|
||||
legalized: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $q0, $q1
|
||||
|
||||
; Should be inverted. Needs two compares.
|
||||
|
||||
; CHECK-LABEL: name: ueq_zero
|
||||
; CHECK: %lhs:_(<2 x s64>) = COPY $q0
|
||||
; CHECK: %zero:_(s64) = G_CONSTANT i64 0
|
||||
; CHECK: %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
|
||||
; CHECK: [[FCMGEZ:%[0-9]+]]:_(<2 x s64>) = G_FCMGEZ %lhs
|
||||
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
|
||||
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
|
||||
; CHECK: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[FCMGEZ]], [[BUILD_VECTOR]]
|
||||
; CHECK: $q0 = COPY [[XOR]](<2 x s64>)
|
||||
; CHECK: RET_ReallyLR implicit $q0
|
||||
%lhs:_(<2 x s64>) = COPY $q0
|
||||
%zero:_(s64) = G_CONSTANT i64 0
|
||||
%zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero, %zero
|
||||
%fcmp:_(<2 x s64>) = G_FCMP floatpred(ult), %lhs(<2 x s64>), %zero_vec
|
||||
$q0 = COPY %fcmp(<2 x s64>)
|
||||
RET_ReallyLR implicit $q0
|
||||
|
||||
...
|
||||
---
|
||||
name: ule
|
||||
alignment: 4
|
||||
legalized: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $q0, $q1
|
||||
|
||||
; Should be inverted. Needs two compares.
|
||||
|
||||
; CHECK-LABEL: name: ule
|
||||
; CHECK: %lhs:_(<2 x s64>) = COPY $q0
|
||||
; CHECK: %rhs:_(<2 x s64>) = COPY $q1
|
||||
; CHECK: [[FCMGT:%[0-9]+]]:_(<2 x s64>) = G_FCMGT %lhs, %rhs(<2 x s64>)
|
||||
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
|
||||
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
|
||||
; CHECK: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[FCMGT]], [[BUILD_VECTOR]]
|
||||
; CHECK: $q0 = COPY [[XOR]](<2 x s64>)
|
||||
; CHECK: RET_ReallyLR implicit $q0
|
||||
%lhs:_(<2 x s64>) = COPY $q0
|
||||
%rhs:_(<2 x s64>) = COPY $q1
|
||||
%fcmp:_(<2 x s64>) = G_FCMP floatpred(ule), %lhs(<2 x s64>), %rhs
|
||||
$q0 = COPY %fcmp(<2 x s64>)
|
||||
RET_ReallyLR implicit $q0
|
||||
|
||||
...
|
||||
---
|
||||
name: ule_zero
|
||||
alignment: 4
|
||||
legalized: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $q0, $q1
|
||||
|
||||
; Should be inverted. Needs two compares.
|
||||
|
||||
; CHECK-LABEL: name: ule_zero
|
||||
; CHECK: %lhs:_(<2 x s64>) = COPY $q0
|
||||
; CHECK: %zero:_(s64) = G_CONSTANT i64 0
|
||||
; CHECK: %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
|
||||
; CHECK: [[FCMGTZ:%[0-9]+]]:_(<2 x s64>) = G_FCMGTZ %lhs
|
||||
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
|
||||
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
|
||||
; CHECK: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[FCMGTZ]], [[BUILD_VECTOR]]
|
||||
; CHECK: $q0 = COPY [[XOR]](<2 x s64>)
|
||||
; CHECK: RET_ReallyLR implicit $q0
|
||||
%lhs:_(<2 x s64>) = COPY $q0
|
||||
%zero:_(s64) = G_CONSTANT i64 0
|
||||
%zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero, %zero
|
||||
%fcmp:_(<2 x s64>) = G_FCMP floatpred(ule), %lhs(<2 x s64>), %zero_vec
|
||||
$q0 = COPY %fcmp(<2 x s64>)
|
||||
RET_ReallyLR implicit $q0
|
||||
|
||||
...
|
||||
---
|
||||
name: ugt
|
||||
alignment: 4
|
||||
legalized: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $q0, $q1
|
||||
|
||||
; Should be inverted. Needs two compares.
|
||||
|
||||
; CHECK-LABEL: name: ugt
|
||||
; CHECK: %lhs:_(<2 x s64>) = COPY $q0
|
||||
; CHECK: %rhs:_(<2 x s64>) = COPY $q1
|
||||
; CHECK: [[FCMGE:%[0-9]+]]:_(<2 x s64>) = G_FCMGE %rhs, %lhs(<2 x s64>)
|
||||
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
|
||||
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
|
||||
; CHECK: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[FCMGE]], [[BUILD_VECTOR]]
|
||||
; CHECK: $q0 = COPY [[XOR]](<2 x s64>)
|
||||
; CHECK: RET_ReallyLR implicit $q0
|
||||
%lhs:_(<2 x s64>) = COPY $q0
|
||||
%rhs:_(<2 x s64>) = COPY $q1
|
||||
%fcmp:_(<2 x s64>) = G_FCMP floatpred(ugt), %lhs(<2 x s64>), %rhs
|
||||
$q0 = COPY %fcmp(<2 x s64>)
|
||||
RET_ReallyLR implicit $q0
|
||||
|
||||
...
|
||||
---
|
||||
name: ugt_zero
|
||||
alignment: 4
|
||||
legalized: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $q0, $q1
|
||||
|
||||
; Should be inverted. Needs two compares.
|
||||
|
||||
; CHECK-LABEL: name: ugt_zero
|
||||
; CHECK: %lhs:_(<2 x s64>) = COPY $q0
|
||||
; CHECK: %zero:_(s64) = G_CONSTANT i64 0
|
||||
; CHECK: %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
|
||||
; CHECK: [[FCMLEZ:%[0-9]+]]:_(<2 x s64>) = G_FCMLEZ %lhs
|
||||
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
|
||||
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
|
||||
; CHECK: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[FCMLEZ]], [[BUILD_VECTOR]]
|
||||
; CHECK: $q0 = COPY [[XOR]](<2 x s64>)
|
||||
; CHECK: RET_ReallyLR implicit $q0
|
||||
%lhs:_(<2 x s64>) = COPY $q0
|
||||
%zero:_(s64) = G_CONSTANT i64 0
|
||||
%zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero, %zero
|
||||
%fcmp:_(<2 x s64>) = G_FCMP floatpred(ugt), %lhs(<2 x s64>), %zero_vec
|
||||
$q0 = COPY %fcmp(<2 x s64>)
|
||||
RET_ReallyLR implicit $q0
|
||||
|
||||
...
|
||||
---
|
||||
name: uge
|
||||
alignment: 4
|
||||
legalized: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $q0, $q1
|
||||
|
||||
; Should be inverted. Needs two compares.
|
||||
|
||||
; CHECK-LABEL: name: uge
|
||||
; CHECK: %lhs:_(<2 x s64>) = COPY $q0
|
||||
; CHECK: %rhs:_(<2 x s64>) = COPY $q1
|
||||
; CHECK: [[FCMGT:%[0-9]+]]:_(<2 x s64>) = G_FCMGT %rhs, %lhs(<2 x s64>)
|
||||
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
|
||||
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
|
||||
; CHECK: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[FCMGT]], [[BUILD_VECTOR]]
|
||||
; CHECK: $q0 = COPY [[XOR]](<2 x s64>)
|
||||
; CHECK: RET_ReallyLR implicit $q0
|
||||
%lhs:_(<2 x s64>) = COPY $q0
|
||||
%rhs:_(<2 x s64>) = COPY $q1
|
||||
%fcmp:_(<2 x s64>) = G_FCMP floatpred(uge), %lhs(<2 x s64>), %rhs
|
||||
$q0 = COPY %fcmp(<2 x s64>)
|
||||
RET_ReallyLR implicit $q0
|
||||
|
||||
...
|
||||
---
|
||||
name: uge_zero
|
||||
alignment: 4
|
||||
legalized: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $q0, $q1
|
||||
|
||||
; Should be inverted. Needs two compares.
|
||||
|
||||
; CHECK-LABEL: name: uge_zero
|
||||
; CHECK: %lhs:_(<2 x s64>) = COPY $q0
|
||||
; CHECK: %zero:_(s64) = G_CONSTANT i64 0
|
||||
; CHECK: %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
|
||||
; CHECK: [[FCMLTZ:%[0-9]+]]:_(<2 x s64>) = G_FCMLTZ %lhs
|
||||
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
|
||||
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
|
||||
; CHECK: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[FCMLTZ]], [[BUILD_VECTOR]]
|
||||
; CHECK: $q0 = COPY [[XOR]](<2 x s64>)
|
||||
; CHECK: RET_ReallyLR implicit $q0
|
||||
%lhs:_(<2 x s64>) = COPY $q0
|
||||
%zero:_(s64) = G_CONSTANT i64 0
|
||||
%zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero, %zero
|
||||
%fcmp:_(<2 x s64>) = G_FCMP floatpred(uge), %lhs(<2 x s64>), %zero_vec
|
||||
$q0 = COPY %fcmp(<2 x s64>)
|
||||
RET_ReallyLR implicit $q0
|
||||
|
||||
...
|
||||
---
|
||||
name: une
|
||||
alignment: 4
|
||||
legalized: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $q0, $q1
|
||||
|
||||
; Negated EQ.
|
||||
|
||||
; CHECK-LABEL: name: une
|
||||
; CHECK: %lhs:_(<2 x s64>) = COPY $q0
|
||||
; CHECK: %rhs:_(<2 x s64>) = COPY $q1
|
||||
; CHECK: [[FCMEQ:%[0-9]+]]:_(<2 x s64>) = G_FCMEQ %lhs, %rhs(<2 x s64>)
|
||||
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
|
||||
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
|
||||
; CHECK: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[FCMEQ]], [[BUILD_VECTOR]]
|
||||
; CHECK: $q0 = COPY [[XOR]](<2 x s64>)
|
||||
; CHECK: RET_ReallyLR implicit $q0
|
||||
%lhs:_(<2 x s64>) = COPY $q0
|
||||
%rhs:_(<2 x s64>) = COPY $q1
|
||||
%fcmp:_(<2 x s64>) = G_FCMP floatpred(une), %lhs(<2 x s64>), %rhs
|
||||
$q0 = COPY %fcmp(<2 x s64>)
|
||||
RET_ReallyLR implicit $q0
|
||||
|
||||
...
|
||||
---
|
||||
name: une_zero
|
||||
alignment: 4
|
||||
legalized: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $q0, $q1
|
||||
|
||||
; Negated EQ.
|
||||
|
||||
; CHECK-LABEL: name: une_zero
|
||||
; CHECK: %lhs:_(<2 x s64>) = COPY $q0
|
||||
; CHECK: %zero:_(s64) = G_CONSTANT i64 0
|
||||
; CHECK: %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
|
||||
; CHECK: [[FCMEQZ:%[0-9]+]]:_(<2 x s64>) = G_FCMEQZ %lhs
|
||||
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
|
||||
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
|
||||
; CHECK: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[FCMEQZ]], [[BUILD_VECTOR]]
|
||||
; CHECK: $q0 = COPY [[XOR]](<2 x s64>)
|
||||
; CHECK: RET_ReallyLR implicit $q0
|
||||
%lhs:_(<2 x s64>) = COPY $q0
|
||||
%zero:_(s64) = G_CONSTANT i64 0
|
||||
%zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero, %zero
|
||||
%fcmp:_(<2 x s64>) = G_FCMP floatpred(une), %lhs(<2 x s64>), %zero_vec
|
||||
$q0 = COPY %fcmp(<2 x s64>)
|
||||
RET_ReallyLR implicit $q0
|
||||
|
||||
...
|
||||
---
|
||||
name: dont_lower_s16
|
||||
alignment: 4
|
||||
legalized: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $q0, $q1
|
||||
|
||||
; CHECK-LABEL: name: dont_lower_s16
|
||||
; CHECK: %lhs:_(<8 x s16>) = COPY $q0
|
||||
; CHECK: %rhs:_(<8 x s16>) = COPY $q1
|
||||
; CHECK: %fcmp:_(<8 x s16>) = G_FCMP floatpred(oeq), %lhs(<8 x s16>), %rhs
|
||||
; CHECK: $q0 = COPY %fcmp(<8 x s16>)
|
||||
; CHECK: RET_ReallyLR implicit $q0
|
||||
%lhs:_(<8 x s16>) = COPY $q0
|
||||
%rhs:_(<8 x s16>) = COPY $q1
|
||||
%fcmp:_(<8 x s16>) = G_FCMP floatpred(oeq), %lhs(<8 x s16>), %rhs
|
||||
$q0 = COPY %fcmp(<8 x s16>)
|
||||
RET_ReallyLR implicit $q0
|
||||
|
|
@ -0,0 +1,162 @@
|
|||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
|
||||
|
||||
...
|
||||
---
|
||||
name: fcmeq
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
body: |
|
||||
bb.0:
|
||||
; CHECK-LABEL: name: fcmeq
|
||||
; CHECK: %lhs:fpr128 = COPY $q0
|
||||
; CHECK: %rhs:fpr128 = COPY $q1
|
||||
; CHECK: %fcmp:fpr128 = FCMEQv2f64 %lhs, %rhs
|
||||
; CHECK: $q0 = COPY %fcmp
|
||||
; CHECK: RET_ReallyLR implicit $q0
|
||||
%lhs:fpr(<2 x s64>) = COPY $q0
|
||||
%rhs:fpr(<2 x s64>) = COPY $q1
|
||||
%fcmp:fpr(<2 x s64>) = G_FCMEQ %lhs, %rhs(<2 x s64>)
|
||||
$q0 = COPY %fcmp(<2 x s64>)
|
||||
RET_ReallyLR implicit $q0
|
||||
|
||||
...
|
||||
---
|
||||
name: fcmge
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
body: |
|
||||
bb.0:
|
||||
; CHECK-LABEL: name: fcmge
|
||||
; CHECK: %lhs:fpr128 = COPY $q0
|
||||
; CHECK: %rhs:fpr128 = COPY $q1
|
||||
; CHECK: %fcmp:fpr128 = FCMGEv2f64 %lhs, %rhs
|
||||
; CHECK: $q0 = COPY %fcmp
|
||||
; CHECK: RET_ReallyLR implicit $q0
|
||||
%lhs:fpr(<2 x s64>) = COPY $q0
|
||||
%rhs:fpr(<2 x s64>) = COPY $q1
|
||||
%fcmp:fpr(<2 x s64>) = G_FCMGE %lhs, %rhs(<2 x s64>)
|
||||
$q0 = COPY %fcmp(<2 x s64>)
|
||||
RET_ReallyLR implicit $q0
|
||||
|
||||
...
|
||||
---
|
||||
name: fcmgt
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
body: |
|
||||
bb.0:
|
||||
; CHECK-LABEL: name: fcmgt
|
||||
; CHECK: %lhs:fpr128 = COPY $q0
|
||||
; CHECK: %rhs:fpr128 = COPY $q1
|
||||
; CHECK: %fcmp:fpr128 = FCMGTv2f64 %lhs, %rhs
|
||||
; CHECK: $q0 = COPY %fcmp
|
||||
; CHECK: RET_ReallyLR implicit $q0
|
||||
%lhs:fpr(<2 x s64>) = COPY $q0
|
||||
%rhs:fpr(<2 x s64>) = COPY $q1
|
||||
%fcmp:fpr(<2 x s64>) = G_FCMGT %lhs, %rhs(<2 x s64>)
|
||||
$q0 = COPY %fcmp(<2 x s64>)
|
||||
RET_ReallyLR implicit $q0
|
||||
|
||||
...
|
||||
---
|
||||
name: fcmeqz
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
body: |
|
||||
bb.0:
|
||||
; CHECK-LABEL: name: fcmeqz
|
||||
; CHECK: %lhs:fpr128 = COPY $q0
|
||||
; CHECK: %fcmp:fpr128 = FCMEQv2i64rz %lhs
|
||||
; CHECK: $q0 = COPY %fcmp
|
||||
; CHECK: RET_ReallyLR implicit $q0
|
||||
%lhs:fpr(<2 x s64>) = COPY $q0
|
||||
%zero:gpr(s64) = G_CONSTANT i64 0
|
||||
%zero_vec:fpr(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
|
||||
%fcmp:fpr(<2 x s64>) = G_FCMEQZ %lhs
|
||||
$q0 = COPY %fcmp(<2 x s64>)
|
||||
RET_ReallyLR implicit $q0
|
||||
|
||||
...
|
||||
---
|
||||
name: fcmgez
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
body: |
|
||||
bb.0:
|
||||
; CHECK-LABEL: name: fcmgez
|
||||
; CHECK: %lhs:fpr128 = COPY $q0
|
||||
; CHECK: %fcmp:fpr128 = FCMGEv2i64rz %lhs
|
||||
; CHECK: $q0 = COPY %fcmp
|
||||
; CHECK: RET_ReallyLR implicit $q0
|
||||
%lhs:fpr(<2 x s64>) = COPY $q0
|
||||
%zero:gpr(s64) = G_CONSTANT i64 0
|
||||
%zero_vec:fpr(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
|
||||
%fcmp:fpr(<2 x s64>) = G_FCMGEZ %lhs
|
||||
$q0 = COPY %fcmp(<2 x s64>)
|
||||
RET_ReallyLR implicit $q0
|
||||
|
||||
...
|
||||
---
|
||||
name: fcmgtz
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
body: |
|
||||
bb.0:
|
||||
; CHECK-LABEL: name: fcmgtz
|
||||
; CHECK: %lhs:fpr128 = COPY $q0
|
||||
; CHECK: %fcmp:fpr128 = FCMGTv2i64rz %lhs
|
||||
; CHECK: $q0 = COPY %fcmp
|
||||
; CHECK: RET_ReallyLR implicit $q0
|
||||
%lhs:fpr(<2 x s64>) = COPY $q0
|
||||
%zero:gpr(s64) = G_CONSTANT i64 0
|
||||
%zero_vec:fpr(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
|
||||
%fcmp:fpr(<2 x s64>) = G_FCMGTZ %lhs
|
||||
$q0 = COPY %fcmp(<2 x s64>)
|
||||
RET_ReallyLR implicit $q0
|
||||
|
||||
...
|
||||
---
|
||||
name: fcmlez
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
body: |
|
||||
bb.0:
|
||||
; CHECK-LABEL: name: fcmlez
|
||||
; CHECK: %lhs:fpr128 = COPY $q0
|
||||
; CHECK: %fcmp:fpr128 = FCMLEv2i64rz %lhs
|
||||
; CHECK: $q0 = COPY %fcmp
|
||||
; CHECK: RET_ReallyLR implicit $q0
|
||||
%lhs:fpr(<2 x s64>) = COPY $q0
|
||||
%zero:gpr(s64) = G_CONSTANT i64 0
|
||||
%zero_vec:fpr(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
|
||||
%fcmp:fpr(<2 x s64>) = G_FCMLEZ %lhs
|
||||
$q0 = COPY %fcmp(<2 x s64>)
|
||||
RET_ReallyLR implicit $q0
|
||||
|
||||
...
|
||||
---
|
||||
name: fcmltz
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
body: |
|
||||
bb.0:
|
||||
; CHECK-LABEL: name: fcmltz
|
||||
; CHECK: %lhs:fpr128 = COPY $q0
|
||||
; CHECK: %fcmp:fpr128 = FCMLTv2i64rz %lhs
|
||||
; CHECK: $q0 = COPY %fcmp
|
||||
; CHECK: RET_ReallyLR implicit $q0
|
||||
%lhs:fpr(<2 x s64>) = COPY $q0
|
||||
%zero:gpr(s64) = G_CONSTANT i64 0
|
||||
%zero_vec:fpr(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
|
||||
%fcmp:fpr(<2 x s64>) = G_FCMLTZ %lhs
|
||||
$q0 = COPY %fcmp(<2 x s64>)
|
||||
RET_ReallyLR implicit $q0
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue