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AMDGPU: Remove DisableInst feature 

I'm not sure why these were bothering to check the instruction
profile, since those profiles should only be used with these
instruction classes.
This commit is contained in:
Matt Arsenault 2019-02-21 14:55:29 -05:00 committed by Matt Arsenault
parent 70726cec5b
commit 79b29d6df7
4 changed files with 13 additions and 15 deletions
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2
llvm/lib/Target/AMDGPU/SIInstrInfo.td
View File

@ -11,8 +11,6 @@ def isWave32 : Predicate<"Subtarget->getWavefrontSize() == 32">,
def isWave64 : Predicate<"Subtarget->getWavefrontSize() == 64">,
AssemblerPredicate <(all_of FeatureWavefrontSize64)>;
def DisableInst : Predicate <"false">, AssemblerPredicate<(all_of FeatureDisable)>;
class GCNPredicateControl : PredicateControl {
Predicate SIAssemblerPredicate = isGFX6GFX7;
Predicate VIAssemblerPredicate = isGFX8GFX9;

4
llvm/lib/Target/AMDGPU/VOP1Instructions.td
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@ -456,7 +456,7 @@ class VOP1_DPP<bits<8> op, VOP1_DPP_Pseudo ps, VOPProfile p = ps.Pfl, bit isDPP1
class VOP1_DPP16<bits<8> op, VOP1_DPP_Pseudo ps, VOPProfile p = ps.Pfl> :
VOP1_DPP<op, ps, p, 1>,
SIMCInstr <ps.PseudoInstr, SIEncodingFamily.GFX10> {
let AssemblerPredicate = !if(p.HasExt, HasDPP16, DisableInst);
let AssemblerPredicate = HasDPP16;
let SubtargetPredicate = HasDPP16;
}
@ -473,7 +473,7 @@ class VOP1_DPP8<bits<8> op, VOP1_Pseudo ps, VOPProfile p = ps.Pfl> :
let Inst{24-17} = !if(p.EmitDst, vdst{7-0}, 0);
let Inst{31-25} = 0x3f;
let AssemblerPredicate = !if(p.HasExt, HasDPP8, DisableInst);
let AssemblerPredicate = HasDPP8;
let SubtargetPredicate = HasDPP8;
}

4
llvm/lib/Target/AMDGPU/VOP2Instructions.td
View File

@ -834,7 +834,7 @@ class VOP2_DPP<bits<6> op, VOP2_DPP_Pseudo ps,
class Base_VOP2_DPP16<bits<6> op, VOP2_DPP_Pseudo ps,
string opName = ps.OpName, VOPProfile p = ps.Pfl> :
VOP2_DPP<op, ps, opName, p, 1> {
let AssemblerPredicate = !if(p.HasExt, HasDPP16, DisableInst);
let AssemblerPredicate = HasDPP16;
let SubtargetPredicate = HasDPP16;
}
@ -860,7 +860,7 @@ class VOP2_DPP8<bits<6> op, VOP2_Pseudo ps,
let Inst{30-25} = op;
let Inst{31} = 0x0;
let AssemblerPredicate = !if(p.HasExt, HasDPP8, DisableInst);
let AssemblerPredicate = HasDPP8;
let SubtargetPredicate = HasDPP8;
}

18
llvm/lib/Target/AMDGPU/VOPInstructions.td
View File

@ -492,8 +492,8 @@ class VOP_SDWA_Pseudo <string opName, VOPProfile P, list<dag> pattern=[]> :
let SDWA = 1;
let Uses = [EXEC];
let SubtargetPredicate = !if(P.HasExtSDWA, HasSDWA, DisableInst);
let AssemblerPredicate = !if(P.HasExtSDWA, HasSDWA, DisableInst);
let SubtargetPredicate = HasSDWA;
let AssemblerPredicate = HasSDWA;
let AsmVariantName = !if(P.HasExtSDWA, AMDGPUAsmVariants.SDWA,
AMDGPUAsmVariants.Disable);
let DecoderNamespace = "SDWA";
@ -542,8 +542,8 @@ class Base_VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> :
let Constraints = ps.Constraints;
let DisableEncoding = ps.DisableEncoding;
let SubtargetPredicate = !if(ps.Pfl.HasExtSDWA9, HasSDWA9, DisableInst);
let AssemblerPredicate = !if(ps.Pfl.HasExtSDWA9, HasSDWA9, DisableInst);
let SubtargetPredicate = HasSDWA9;
let AssemblerPredicate = HasSDWA9;
let AsmVariantName = !if(ps.Pfl.HasExtSDWA9, AMDGPUAsmVariants.SDWA9,
AMDGPUAsmVariants.Disable);
let DecoderNamespace = "SDWA9";
@ -561,8 +561,8 @@ class VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> :
SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SDWA9>;
class Base_VOP_SDWA10_Real<VOP_SDWA_Pseudo ps> : Base_VOP_SDWA9_Real<ps> {
let SubtargetPredicate = !if(ps.Pfl.HasExtSDWA9, HasSDWA10, DisableInst);
let AssemblerPredicate = !if(ps.Pfl.HasExtSDWA9, HasSDWA10, DisableInst);
let SubtargetPredicate = HasSDWA10;
let AssemblerPredicate = HasSDWA10;
let DecoderNamespace = "SDWA10";
}
@ -615,7 +615,7 @@ class VOP_DPP_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
let AsmMatchConverter = !if(!eq(P.HasModifiers,1), "cvtDPP", "");
let SubtargetPredicate = HasDPP;
let AssemblerPredicate = !if(P.HasExtDPP, HasDPP, DisableInst);
let AssemblerPredicate = HasDPP;
let AsmVariantName = !if(P.HasExtDPP, AMDGPUAsmVariants.DPP,
AMDGPUAsmVariants.Disable);
let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $vdst", "");
@ -670,7 +670,7 @@ class VOP_DPP <string OpName, VOPProfile P, bit IsDPP16,
let AsmMatchConverter = !if(!eq(P.HasModifiers,1), "cvtDPP", "");
let SubtargetPredicate = HasDPP;
let AssemblerPredicate = !if(P.HasExtDPP, HasDPP, DisableInst);
let AssemblerPredicate = HasDPP;
let AsmVariantName = !if(P.HasExtDPP, AMDGPUAsmVariants.DPP,
AMDGPUAsmVariants.Disable);
let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $vdst", "");
@ -702,7 +702,7 @@ class VOP_DPP8<string OpName, VOPProfile P> :
let AsmMatchConverter = "cvtDPP8";
let SubtargetPredicate = HasDPP8;
let AssemblerPredicate = !if(P.HasExt, HasDPP8, DisableInst);
let AssemblerPredicate = HasDPP8;
let AsmVariantName = !if(P.HasExt, AMDGPUAsmVariants.DPP,
AMDGPUAsmVariants.Disable);
let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $vdst", "");