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[LoongArch] Fix several instruction definition errors in initial patches 

This patch corrects some instruction definitions that I incorrectly wrote
in initial patches including bstr{ins/pick}.{w/d}, ll.{w/d} and sc.{w/d}.

Reviewed By: xen0n

Differential Revision: https://reviews.llvm.org/D119817
This commit is contained in:
Weining Lu 2022-02-18 10:04:28 +08:00
parent 1d91537ce8
commit 79b0fa08e0
3 changed files with 30 additions and 25 deletions
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20
llvm/lib/Target/LoongArch/LoongArchInstrFormats.td
View File

@ -256,34 +256,34 @@ class FmtI26<bits<6> op, dag outs, dag ins, string asmstr,
}
// FmtBSTR_W
// <opcode[11:1] | msb | opcode[0] | lsb | rj | rd>
// <opcode[11:1] | msbw | opcode[0] | lsbw | rj | rd>
class FmtBSTR_W<bits<12> op, dag outs, dag ins, string asmstr,
list<dag> pattern = []> : LAInst<outs, ins, asmstr, pattern> {
bits<5> msb;
bits<5> lsb;
bits<5> msbw;
bits<5> lsbw;
bits<5> rj;
bits<5> rd;
let Inst{31-21} = op{11-1};
let Inst{20-16} = msb;
let Inst{20-16} = msbw;
let Inst{15} = op{0};
let Inst{14-10} = lsb;
let Inst{14-10} = lsbw;
let Inst{9-5} = rj;
let Inst{4-0} = rd;
}
// FmtBSTR_D
// <opcode | msb | lsb | rj | rd>
// <opcode | msbd | lsbd | rj | rd>
class FmtBSTR_D<bits<10> op, dag outs, dag ins, string asmstr,
list<dag> pattern = []> : LAInst<outs, ins, asmstr, pattern> {
bits<6> msb;
bits<6> lsb;
bits<6> msbd;
bits<6> lsbd;
bits<5> rj;
bits<5> rd;
let Inst{31-22} = op;
let Inst{21-16} = msb;
let Inst{15-10} = lsb;
let Inst{21-16} = msbd;
let Inst{15-10} = lsbd;
let Inst{9-5} = rj;
let Inst{4-0} = rd;
}

31
llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
View File

@ -86,13 +86,6 @@ class ALU_1RI20<bits<7> op, string opstr, Operand ImmOpnd>
: Fmt1RI20<op, (outs GPR:$rd), (ins ImmOpnd:$imm20),
!strconcat(opstr, "\t$rd, $imm20")>;
class ALU_BSTRW<bits<12> op, string opstr, Operand ImmOpnd>
: FmtBSTR_W<op, (outs GPR:$rd), (ins GPR:$rj, ImmOpnd:$msb, ImmOpnd:$lsb),
!strconcat(opstr, "\t$rd, $rj, $msb, $lsb")>;
class ALU_BSTRD<bits<10> op, string opstr, Operand ImmOpnd>
: FmtBSTR_D<op, (outs GPR:$rd), (ins GPR:$rj, ImmOpnd:$msb, ImmOpnd:$lsb),
!strconcat(opstr, "\t$rd, $rj, $msb, $lsb")>;
class MISC_I15<bits<17> op, string opstr>
: FmtI15<op, (outs), (ins uimm15:$imm15), !strconcat(opstr, "\t$imm15")>;
@ -150,12 +143,12 @@ class AM_3R<bits<17> op, string opstr>
let mayLoad = 1 in
class LLBase<bits<8> op, string opstr>
: Fmt2RI14<op, (outs GPR:$rd), (ins GPR:$rj, simm14:$imm14),
: Fmt2RI14<op, (outs GPR:$rd), (ins GPR:$rj, simm14_lsl2:$imm14),
!strconcat(opstr, "\t$rd, $rj, $imm14")>;
let mayStore = 1, Constraints = "$rd = $dst" in
class SCBase<bits<8> op, string opstr>
: Fmt2RI14<op, (outs GPR:$dst), (ins GPR:$rd, GPR:$rj, simm14:$imm14),
: Fmt2RI14<op, (outs GPR:$dst), (ins GPR:$rd, GPR:$rj, simm14_lsl2:$imm14),
!strconcat(opstr, "\t$rd, $rj, $imm14")>;
//===----------------------------------------------------------------------===//
@ -214,8 +207,14 @@ def BYTEPICK_W : ALU_3RI2<0b000000000000100, "bytepick.w", uimm2>;
def REVB_2H : ALU_2R<0b0000000000000000001100, "revb.2h">;
def BITREV_4B : ALU_2R<0b0000000000000000010010, "bitrev.4b">;
def BITREV_W : ALU_2R<0b0000000000000000010100, "bitrev.w">;
def BSTRINS_W : ALU_BSTRW<0b000000000110, "bstrins.w", uimm5>;
def BSTRPICK_W : ALU_BSTRW<0b000000000111, "bstrpick.w", uimm5>;
let Constraints = "$rd = $dst" in {
def BSTRINS_W : FmtBSTR_W<0b000000000110, (outs GPR:$dst),
(ins GPR:$rd, GPR:$rj, uimm5:$msbw, uimm5:$lsbw),
"bstrins.w\t$rd, $rj, $msbw, $lsbw">;
}
def BSTRPICK_W : FmtBSTR_W<0b000000000111, (outs GPR:$rd),
(ins GPR:$rj, uimm5:$msbw, uimm5:$lsbw),
"bstrpick.w\t$rd, $rj, $msbw, $lsbw">;
def MASKEQZ : ALU_3R<0b00000000000100110, "maskeqz">;
def MASKNEZ : ALU_3R<0b00000000000100111, "masknez">;
@ -309,8 +308,14 @@ def REVH_2W : ALU_2R<0b0000000000000000010000, "revh.2w">;
def REVH_D : ALU_2R<0b0000000000000000010001, "revh.d">;
def BITREV_8B : ALU_2R<0b0000000000000000010011, "bitrev.8b">;
def BITREV_D : ALU_2R<0b0000000000000000010101, "bitrev.d">;
def BSTRINS_D : ALU_BSTRD<0b0000000010, "bstrins.d", uimm6>;
def BSTRPICK_D : ALU_BSTRD<0b0000000011, "bstrpick.d", uimm6>;
let Constraints = "$rd = $dst" in {
def BSTRINS_D : FmtBSTR_D<0b0000000010, (outs GPR:$dst),
(ins GPR:$rd, GPR:$rj, uimm6:$msbd, uimm6:$lsbd),
"bstrins.d\t$rd, $rj, $msbd, $lsbd">;
}
def BSTRPICK_D : FmtBSTR_D<0b0000000011, (outs GPR:$rd),
(ins GPR:$rj, uimm6:$msbd, uimm6:$lsbd),
"bstrpick.d\t$rd, $rj, $msbd, $lsbd">;
// Common Memory Access Instructions for 64-bits
def LD_WU : LOAD_2RI12<0b0010101010, "ld.wu">;

4
llvm/test/CodeGen/LoongArch/misc.mir
View File

@ -94,7 +94,7 @@ body: |
name: test_BSTRINS_W
body: |
bb.0:
$r4 = BSTRINS_W $r5, 7, 2
$r4 = BSTRINS_W $r4, $r5, 7, 2
...
---
# CHECK-LABEL: test_BSTRPICK_W:
@ -122,7 +122,7 @@ body: |
name: test_BSTRINS_D
body: |
bb.0:
$r4 = BSTRINS_D $r5, 7, 2
$r4 = BSTRINS_D $r4, $r5, 7, 2
...
---
# CHECK-LABEL: test_BSTRPICK_D: