forked from OSchip/llvm-project
Add a description of the status of segmented stacks.
llvm-svn: 145201
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@ -2321,6 +2321,20 @@ is the key:</p>
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<td class="unknown"></td> <!-- XCore -->
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</tr>
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<tr>
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<td><a href="#feat_segstacks">segmented stacks</a></td>
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<td class="no"></td> <!-- ARM -->
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<td class="no"></td> <!-- CellSPU -->
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<td class="no"></td> <!-- MBlaze -->
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<td class="no"></td> <!-- MSP430 -->
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<td class="no"></td> <!-- Mips -->
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<td class="no"></td> <!-- PTX -->
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<td class="no"></td> <!-- PowerPC -->
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<td class="no"></td> <!-- Sparc -->
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<td class="partial"><a href="#feat_segstacks_x86">*</a></td> <!-- X86 -->
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<td class="no"></td> <!-- XCore -->
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</tr>
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</table>
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@ -2404,6 +2418,22 @@ more more details</a>.</p>
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</div>
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<!-- _______________________________________________________________________ -->
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<h4 id="feat_segstacks">Segmented Stacks</h4>
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<div>
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<p>This box indicates whether the target supports segmented stacks. This
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replaces the traditional large C stack with many linked segments. It
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is compatible with the <a href="http://gcc.gnu.org/wiki/SplitStacks">gcc
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implementation</a> used by the Go front end.</p>
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<p id="feat_segstacks_x86">Basic support exits on the X86 backend. Currently
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vararg don't work and the object files are not marked the way the gold
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linker expects, but simple Go program can be built by dragonegg.</p>
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</div>
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</div>
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<!-- ======================================================================= -->
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