forked from OSchip/llvm-project
[X86] Autogenerate complete checks. NFC
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@ -1,3 +1,4 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mcpu=penryn | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -mcpu=sandybridge | FileCheck %s --check-prefix=AVX
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; RUN: llc < %s -mcpu=haswell | FileCheck %s --check-prefix=AVX2
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@ -7,13 +8,18 @@ target triple = "x86_64-unknown-unknown"
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define <4 x i32> @zero_vector() {
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; SSE-LABEL: zero_vector:
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; SSE: xorps %xmm0, %xmm0
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; SSE: # %bb.0:
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; SSE-NEXT: xorps %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: zero_vector:
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; AVX: vxorps %xmm0, %xmm0, %xmm0
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; AVX: # %bb.0:
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; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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;
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; AVX2-LABEL: zero_vector:
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; AVX2: vxorps %xmm0, %xmm0, %xmm0
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; AVX2: # %bb.0:
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; AVX2-NEXT: vxorps %xmm0, %xmm0, %xmm0
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; AVX2-NEXT: retq
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%zero = insertelement <4 x i32> undef, i32 0, i32 0
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%splat = shufflevector <4 x i32> %zero, <4 x i32> undef, <4 x i32> zeroinitializer
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@ -26,13 +32,18 @@ define <4 x i32> @zero_vector() {
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; However, this is not the current preferred lowering.
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define <4 x i32> @const_vector() {
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; SSE-LABEL: const_vector:
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; SSE: movaps {{.*}}, %xmm0 # xmm0 = [42,42,42,42]
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; SSE: # %bb.0:
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; SSE-NEXT: movaps {{.*#+}} xmm0 = [42,42,42,42]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: const_vector:
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; AVX: vmovaps {{.*}}, %xmm0 # xmm0 = [42,42,42,42]
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; AVX: # %bb.0:
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; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [42,42,42,42]
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; AVX-NEXT: retq
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;
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; AVX2-LABEL: const_vector:
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; AVX2: vbroadcastss {{[^%].*}}, %xmm0
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; AVX2: # %bb.0:
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; AVX2-NEXT: vbroadcastss {{.*#+}} xmm0 = [42,42,42,42]
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; AVX2-NEXT: retq
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%const = insertelement <4 x i32> undef, i32 42, i32 0
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%splat = shufflevector <4 x i32> %const, <4 x i32> undef, <4 x i32> zeroinitializer
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