forked from OSchip/llvm-project
[X86] Improve readability of test/CodeGen/X86/lzcnt-zext-cmp.ll by adding a common check prefix ALL. NFC.
llvm-svn: 294938
This commit is contained in:
Pierre Gousseau
parent
f77219e035
commit
796e0d6df1
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@ -1,26 +1,19 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; Test patterns which generates lzcnt instructions.
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; Eg: zext(or(setcc(cmp), setcc(cmp))) -> shr(or(lzcnt, lzcnt))
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; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=btver2 | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=btver2 -mattr=-fast-lzcnt | FileCheck --check-prefix=NOFASTLZCNT %s
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; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=znver1 | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=znver1 -mattr=-fast-lzcnt | FileCheck --check-prefix=NOFASTLZCNT %s
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; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=btver2 | FileCheck --check-prefix=ALL --check-prefix=FASTLZCNT %s
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; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=btver2 -mattr=-fast-lzcnt | FileCheck --check-prefix=ALL --check-prefix=NOFASTLZCNT %s
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; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=znver1 | FileCheck --check-prefix=ALL --check-prefix=FASTLZCNT %s
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; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=znver1 -mattr=-fast-lzcnt | FileCheck --check-prefix=ALL --check-prefix=NOFASTLZCNT %s
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; Test one 32-bit input, output is 32-bit, no transformations expected.
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define i32 @test_zext_cmp0(i32 %a) {
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; CHECK-LABEL: test_zext_cmp0:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: testl %edi, %edi
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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;
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; NOFASTLZCNT-LABEL: test_zext_cmp0:
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; NOFASTLZCNT: # BB#0: # %entry
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; NOFASTLZCNT-NEXT: xorl %eax, %eax
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; NOFASTLZCNT-NEXT: testl %edi, %edi
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; NOFASTLZCNT-NEXT: sete %al
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; NOFASTLZCNT-NEXT: retq
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; ALL-LABEL: test_zext_cmp0:
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; ALL: # BB#0: # %entry
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; ALL-NEXT: xorl %eax, %eax
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; ALL-NEXT: testl %edi, %edi
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; ALL-NEXT: sete %al
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; ALL-NEXT: retq
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entry:
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%cmp = icmp eq i32 %a, 0
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%conv = zext i1 %cmp to i32
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@ -29,13 +22,13 @@ entry:
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; Test two 32-bit inputs, output is 32-bit.
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define i32 @test_zext_cmp1(i32 %a, i32 %b) {
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; CHECK-LABEL: test_zext_cmp1:
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; CHECK: # BB#0:
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; CHECK-NEXT: lzcntl %edi, %ecx
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; CHECK-NEXT: lzcntl %esi, %eax
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; CHECK-NEXT: orl %ecx, %eax
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; CHECK-NEXT: shrl $5, %eax
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; CHECK-NEXT: retq
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; FASTLZCNT-LABEL: test_zext_cmp1:
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; FASTLZCNT: # BB#0:
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; FASTLZCNT-NEXT: lzcntl %edi, %ecx
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; FASTLZCNT-NEXT: lzcntl %esi, %eax
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; FASTLZCNT-NEXT: orl %ecx, %eax
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; FASTLZCNT-NEXT: shrl $5, %eax
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; FASTLZCNT-NEXT: retq
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;
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; NOFASTLZCNT-LABEL: test_zext_cmp1:
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; NOFASTLZCNT: # BB#0:
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@ -55,13 +48,13 @@ define i32 @test_zext_cmp1(i32 %a, i32 %b) {
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; Test two 64-bit inputs, output is 64-bit.
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define i64 @test_zext_cmp2(i64 %a, i64 %b) {
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; CHECK-LABEL: test_zext_cmp2:
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; CHECK: # BB#0:
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; CHECK-NEXT: lzcntq %rdi, %rcx
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; CHECK-NEXT: lzcntq %rsi, %rax
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; CHECK-NEXT: orl %ecx, %eax
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; CHECK-NEXT: shrl $6, %eax
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; CHECK-NEXT: retq
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; FASTLZCNT-LABEL: test_zext_cmp2:
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; FASTLZCNT: # BB#0:
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; FASTLZCNT-NEXT: lzcntq %rdi, %rcx
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; FASTLZCNT-NEXT: lzcntq %rsi, %rax
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; FASTLZCNT-NEXT: orl %ecx, %eax
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; FASTLZCNT-NEXT: shrl $6, %eax
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; FASTLZCNT-NEXT: retq
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;
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; NOFASTLZCNT-LABEL: test_zext_cmp2:
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; NOFASTLZCNT: # BB#0:
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@ -83,27 +76,16 @@ define i64 @test_zext_cmp2(i64 %a, i64 %b) {
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; The transform is disabled for the 16-bit case, as we still have to clear the
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; upper 16-bits, adding one more instruction.
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define i16 @test_zext_cmp3(i16 %a, i16 %b) {
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; CHECK-LABEL: test_zext_cmp3:
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; CHECK: # BB#0:
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; CHECK-NEXT: testw %di, %di
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: testw %si, %si
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; CHECK-NEXT: sete %cl
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; CHECK-NEXT: orb %al, %cl
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; CHECK-NEXT: movzbl %cl, %eax
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; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
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; CHECK-NEXT: retq
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;
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; NOFASTLZCNT-LABEL: test_zext_cmp3:
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; NOFASTLZCNT: # BB#0:
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; NOFASTLZCNT-NEXT: testw %di, %di
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; NOFASTLZCNT-NEXT: sete %al
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; NOFASTLZCNT-NEXT: testw %si, %si
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; NOFASTLZCNT-NEXT: sete %cl
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; NOFASTLZCNT-NEXT: orb %al, %cl
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; NOFASTLZCNT-NEXT: movzbl %cl, %eax
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; NOFASTLZCNT-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
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; NOFASTLZCNT-NEXT: retq
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; ALL-LABEL: test_zext_cmp3:
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; ALL: # BB#0:
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; ALL-NEXT: testw %di, %di
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; ALL-NEXT: sete %al
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; ALL-NEXT: testw %si, %si
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; ALL-NEXT: sete %cl
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; ALL-NEXT: orb %al, %cl
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; ALL-NEXT: movzbl %cl, %eax
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; ALL-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
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; ALL-NEXT: retq
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%cmp = icmp eq i16 %a, 0
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%cmp1 = icmp eq i16 %b, 0
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%or = or i1 %cmp, %cmp1
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@ -113,13 +95,13 @@ define i16 @test_zext_cmp3(i16 %a, i16 %b) {
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; Test two 32-bit inputs, output is 64-bit.
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define i64 @test_zext_cmp4(i32 %a, i32 %b) {
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; CHECK-LABEL: test_zext_cmp4:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: lzcntl %edi, %ecx
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; CHECK-NEXT: lzcntl %esi, %eax
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; CHECK-NEXT: orl %ecx, %eax
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; CHECK-NEXT: shrl $5, %eax
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; CHECK-NEXT: retq
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; FASTLZCNT-LABEL: test_zext_cmp4:
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; FASTLZCNT: # BB#0: # %entry
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; FASTLZCNT-NEXT: lzcntl %edi, %ecx
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; FASTLZCNT-NEXT: lzcntl %esi, %eax
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; FASTLZCNT-NEXT: orl %ecx, %eax
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; FASTLZCNT-NEXT: shrl $5, %eax
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; FASTLZCNT-NEXT: retq
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;
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; NOFASTLZCNT-LABEL: test_zext_cmp4:
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; NOFASTLZCNT: # BB#0: # %entry
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@ -140,14 +122,14 @@ entry:
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; Test two 64-bit inputs, output is 32-bit.
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define i32 @test_zext_cmp5(i64 %a, i64 %b) {
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; CHECK-LABEL: test_zext_cmp5:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: lzcntq %rdi, %rcx
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; CHECK-NEXT: lzcntq %rsi, %rax
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; CHECK-NEXT: orl %ecx, %eax
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; CHECK-NEXT: shrl $6, %eax
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; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill>
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; CHECK-NEXT: retq
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; FASTLZCNT-LABEL: test_zext_cmp5:
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; FASTLZCNT: # BB#0: # %entry
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; FASTLZCNT-NEXT: lzcntq %rdi, %rcx
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; FASTLZCNT-NEXT: lzcntq %rsi, %rax
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; FASTLZCNT-NEXT: orl %ecx, %eax
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; FASTLZCNT-NEXT: shrl $6, %eax
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; FASTLZCNT-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill>
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; FASTLZCNT-NEXT: retq
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;
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; NOFASTLZCNT-LABEL: test_zext_cmp5:
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; NOFASTLZCNT: # BB#0: # %entry
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@ -168,15 +150,15 @@ entry:
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; Test three 32-bit inputs, output is 32-bit.
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define i32 @test_zext_cmp6(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: test_zext_cmp6:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: lzcntl %edi, %eax
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; CHECK-NEXT: lzcntl %esi, %ecx
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; CHECK-NEXT: orl %eax, %ecx
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; CHECK-NEXT: lzcntl %edx, %eax
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; CHECK-NEXT: orl %ecx, %eax
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; CHECK-NEXT: shrl $5, %eax
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; CHECK-NEXT: retq
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; FASTLZCNT-LABEL: test_zext_cmp6:
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; FASTLZCNT: # BB#0: # %entry
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; FASTLZCNT-NEXT: lzcntl %edi, %eax
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; FASTLZCNT-NEXT: lzcntl %esi, %ecx
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; FASTLZCNT-NEXT: orl %eax, %ecx
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; FASTLZCNT-NEXT: lzcntl %edx, %eax
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; FASTLZCNT-NEXT: orl %ecx, %eax
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; FASTLZCNT-NEXT: shrl $5, %eax
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; FASTLZCNT-NEXT: retq
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;
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; NOFASTLZCNT-LABEL: test_zext_cmp6:
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; NOFASTLZCNT: # BB#0: # %entry
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@ -203,15 +185,15 @@ entry:
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; Test three 32-bit inputs, output is 32-bit, but compared to test_zext_cmp6 test,
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; %.cmp2 inputs' order is inverted.
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define i32 @test_zext_cmp7(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: test_zext_cmp7:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: lzcntl %edi, %eax
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; CHECK-NEXT: lzcntl %esi, %ecx
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; CHECK-NEXT: orl %eax, %ecx
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; CHECK-NEXT: lzcntl %edx, %eax
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; CHECK-NEXT: orl %ecx, %eax
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; CHECK-NEXT: shrl $5, %eax
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; CHECK-NEXT: retq
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; FASTLZCNT-LABEL: test_zext_cmp7:
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; FASTLZCNT: # BB#0: # %entry
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; FASTLZCNT-NEXT: lzcntl %edi, %eax
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; FASTLZCNT-NEXT: lzcntl %esi, %ecx
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; FASTLZCNT-NEXT: orl %eax, %ecx
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; FASTLZCNT-NEXT: lzcntl %edx, %eax
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; FASTLZCNT-NEXT: orl %ecx, %eax
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; FASTLZCNT-NEXT: shrl $5, %eax
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; FASTLZCNT-NEXT: retq
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;
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; NOFASTLZCNT-LABEL: test_zext_cmp7:
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; NOFASTLZCNT: # BB#0: # %entry
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@ -237,17 +219,17 @@ entry:
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; Test four 32-bit inputs, output is 32-bit.
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define i32 @test_zext_cmp8(i32 %a, i32 %b, i32 %c, i32 %d) {
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; CHECK-LABEL: test_zext_cmp8:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: lzcntl %edi, %eax
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; CHECK-NEXT: lzcntl %esi, %esi
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; CHECK-NEXT: lzcntl %edx, %edx
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; CHECK-NEXT: orl %eax, %esi
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; CHECK-NEXT: lzcntl %ecx, %eax
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; CHECK-NEXT: orl %edx, %eax
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; CHECK-NEXT: orl %esi, %eax
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; CHECK-NEXT: shrl $5, %eax
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; CHECK-NEXT: retq
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; FASTLZCNT-LABEL: test_zext_cmp8:
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; FASTLZCNT: # BB#0: # %entry
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; FASTLZCNT-NEXT: lzcntl %edi, %eax
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; FASTLZCNT-NEXT: lzcntl %esi, %esi
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; FASTLZCNT-NEXT: lzcntl %edx, %edx
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; FASTLZCNT-NEXT: orl %eax, %esi
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; FASTLZCNT-NEXT: lzcntl %ecx, %eax
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; FASTLZCNT-NEXT: orl %edx, %eax
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; FASTLZCNT-NEXT: orl %esi, %eax
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; FASTLZCNT-NEXT: shrl $5, %eax
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; FASTLZCNT-NEXT: retq
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;
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; NOFASTLZCNT-LABEL: test_zext_cmp8:
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; NOFASTLZCNT: # BB#0: # %entry
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@ -278,15 +260,15 @@ entry:
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; Test one 32-bit input, one 64-bit input, output is 32-bit.
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define i32 @test_zext_cmp9(i32 %a, i64 %b) {
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; CHECK-LABEL: test_zext_cmp9:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: lzcntq %rsi, %rax
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; CHECK-NEXT: lzcntl %edi, %ecx
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; CHECK-NEXT: shrl $5, %ecx
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; CHECK-NEXT: shrl $6, %eax
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; CHECK-NEXT: orl %ecx, %eax
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; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill>
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; CHECK-NEXT: retq
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; FASTLZCNT-LABEL: test_zext_cmp9:
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; FASTLZCNT: # BB#0: # %entry
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; FASTLZCNT-NEXT: lzcntq %rsi, %rax
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; FASTLZCNT-NEXT: lzcntl %edi, %ecx
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; FASTLZCNT-NEXT: shrl $5, %ecx
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; FASTLZCNT-NEXT: shrl $6, %eax
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; FASTLZCNT-NEXT: orl %ecx, %eax
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; FASTLZCNT-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill>
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; FASTLZCNT-NEXT: retq
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;
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; NOFASTLZCNT-LABEL: test_zext_cmp9:
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; NOFASTLZCNT: # BB#0: # %entry
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@ -307,25 +289,15 @@ entry:
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; Test 2 128-bit inputs, output is 32-bit, no transformations expected.
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define i32 @test_zext_cmp10(i64 %a.coerce0, i64 %a.coerce1, i64 %b.coerce0, i64 %b.coerce1) {
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; CHECK-LABEL: test_zext_cmp10:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: orq %rsi, %rdi
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: orq %rcx, %rdx
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; CHECK-NEXT: sete %cl
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; CHECK-NEXT: orb %al, %cl
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; CHECK-NEXT: movzbl %cl, %eax
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; CHECK-NEXT: retq
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;
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; NOFASTLZCNT-LABEL: test_zext_cmp10:
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; NOFASTLZCNT: # BB#0: # %entry
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; NOFASTLZCNT-NEXT: orq %rsi, %rdi
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; NOFASTLZCNT-NEXT: sete %al
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; NOFASTLZCNT-NEXT: orq %rcx, %rdx
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; NOFASTLZCNT-NEXT: sete %cl
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; NOFASTLZCNT-NEXT: orb %al, %cl
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; NOFASTLZCNT-NEXT: movzbl %cl, %eax
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; NOFASTLZCNT-NEXT: retq
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; ALL-LABEL: test_zext_cmp10:
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; ALL: # BB#0: # %entry
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; ALL-NEXT: orq %rsi, %rdi
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; ALL-NEXT: sete %al
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; ALL-NEXT: orq %rcx, %rdx
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; ALL-NEXT: sete %cl
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; ALL-NEXT: orb %al, %cl
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; ALL-NEXT: movzbl %cl, %eax
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; ALL-NEXT: retq
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entry:
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%a.sroa.2.0.insert.ext = zext i64 %a.coerce1 to i128
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%a.sroa.2.0.insert.shift = shl nuw i128 %a.sroa.2.0.insert.ext, 64
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@ -344,27 +316,17 @@ entry:
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; PR31902 Fix a crash in combineOrCmpEqZeroToCtlzSrl under fast math.
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define i32 @test_zext_cmp11(double %a, double %b) "no-nans-fp-math"="true" {
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; CHECK-LABEL: test_zext_cmp11:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
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; CHECK-NEXT: vucomisd %xmm2, %xmm0
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: vucomisd %xmm2, %xmm1
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; CHECK-NEXT: sete %cl
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; CHECK-NEXT: orb %al, %cl
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; CHECK-NEXT: movzbl %cl, %eax
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; CHECK-NEXT: retq
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;
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; NOFASTLZCNT-LABEL: test_zext_cmp11:
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; NOFASTLZCNT: # BB#0: # %entry
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; NOFASTLZCNT-NEXT: vxorps %xmm2, %xmm2, %xmm2
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; NOFASTLZCNT-NEXT: vucomisd %xmm2, %xmm0
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; NOFASTLZCNT-NEXT: sete %al
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; NOFASTLZCNT-NEXT: vucomisd %xmm2, %xmm1
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; NOFASTLZCNT-NEXT: sete %cl
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; NOFASTLZCNT-NEXT: orb %al, %cl
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; NOFASTLZCNT-NEXT: movzbl %cl, %eax
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; NOFASTLZCNT-NEXT: retq
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; ALL-LABEL: test_zext_cmp11:
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; ALL: # BB#0: # %entry
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; ALL-NEXT: vxorps %xmm2, %xmm2, %xmm2
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; ALL-NEXT: vucomisd %xmm2, %xmm0
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; ALL-NEXT: sete %al
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; ALL-NEXT: vucomisd %xmm2, %xmm1
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; ALL-NEXT: sete %cl
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; ALL-NEXT: orb %al, %cl
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; ALL-NEXT: movzbl %cl, %eax
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; ALL-NEXT: retq
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entry:
|
||||
%cmp = fcmp fast oeq double %a, 0.000000e+00
|
||||
%cmp1 = fcmp fast oeq double %b, 0.000000e+00
|
||||
|
|
|
|||
Loading…
Reference in New Issue