forked from OSchip/llvm-project
R600/SI: Fix MIN3/MAX3 on VI, define MED3
llvm-svn: 227213
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@ -1658,27 +1658,34 @@ defm V_ALIGNBYTE_B32 : VOP3Inst <vop3<0x14f, 0x1cf>, "v_alignbyte_b32",
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VOP_I32_I32_I32_I32
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>;
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defm V_MIN3_F32 : VOP3Inst <vop3<0x151>, "v_min3_f32",
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defm V_MIN3_F32 : VOP3Inst <vop3<0x151, 0x1d0>, "v_min3_f32",
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VOP_F32_F32_F32_F32, AMDGPUfmin3>;
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defm V_MIN3_I32 : VOP3Inst <vop3<0x152>, "v_min3_i32",
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defm V_MIN3_I32 : VOP3Inst <vop3<0x152, 0x1d1>, "v_min3_i32",
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VOP_I32_I32_I32_I32, AMDGPUsmin3
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>;
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defm V_MIN3_U32 : VOP3Inst <vop3<0x153>, "v_min3_u32",
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defm V_MIN3_U32 : VOP3Inst <vop3<0x153, 0x1d2>, "v_min3_u32",
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VOP_I32_I32_I32_I32, AMDGPUumin3
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>;
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defm V_MAX3_F32 : VOP3Inst <vop3<0x154>, "v_max3_f32",
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defm V_MAX3_F32 : VOP3Inst <vop3<0x154, 0x1d3>, "v_max3_f32",
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VOP_F32_F32_F32_F32, AMDGPUfmax3
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>;
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defm V_MAX3_I32 : VOP3Inst <vop3<0x155>, "v_max3_i32",
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defm V_MAX3_I32 : VOP3Inst <vop3<0x155, 0x1d4>, "v_max3_i32",
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VOP_I32_I32_I32_I32, AMDGPUsmax3
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>;
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defm V_MAX3_U32 : VOP3Inst <vop3<0x156>, "v_max3_u32",
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defm V_MAX3_U32 : VOP3Inst <vop3<0x156, 0x1d5>, "v_max3_u32",
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VOP_I32_I32_I32_I32, AMDGPUumax3
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>;
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//def V_MED3_F32 : VOP3_MED3 <0x00000157, "v_med3_f32", []>;
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//def V_MED3_I32 : VOP3_MED3 <0x00000158, "v_med3_i32", []>;
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//def V_MED3_U32 : VOP3_MED3 <0x00000159, "v_med3_u32", []>;
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defm V_MED3_F32 : VOP3Inst <vop3<0x157, 0x1d6>, "v_med3_f32",
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VOP_F32_F32_F32_F32
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>;
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defm V_MED3_I32 : VOP3Inst <vop3<0x158, 0x1d7>, "v_med3_i32",
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VOP_I32_I32_I32_I32
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>;
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defm V_MED3_U32 : VOP3Inst <vop3<0x159, 0x1d8>, "v_med3_u32",
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VOP_I32_I32_I32_I32
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>;
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//def V_SAD_U8 : VOP3_U8 <0x0000015a, "v_sad_u8", []>;
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//def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "v_sad_hi_u8", []>;
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//def V_SAD_U16 : VOP3_U16 <0x0000015c, "v_sad_u16", []>;
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