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[RISCV] Address clang-tidy warnings in RISCVTargetMachine. NFC.

This commit is contained in:
Fraser Cormack 2020-12-18 21:49:14 +00:00
parent 37d0dda739
commit 7948cd11d1
2 changed files with 6 additions and 8 deletions
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12
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
View File

@ -35,7 +35,7 @@ using namespace llvm;
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target());
auto PR = PassRegistry::getPassRegistry();
auto *PR = PassRegistry::getPassRegistry();
initializeGlobalISel(*PR);
initializeRISCVMergeBaseOffsetOptPass(*PR);
initializeRISCVExpandPseudoPass(*PR);
@ -43,12 +43,10 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
}
static StringRef computeDataLayout(const Triple &TT) {
if (TT.isArch64Bit()) {
if (TT.isArch64Bit())
return "e-m:e-p:64:64-i64:64-i128:128-n64-S128";
} else {
assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
return "e-m:e-p:32:32-i64:64-n32-S128";
}
assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
return "e-m:e-p:32:32-i64:64-n32-S128";
}
static Reloc::Model getEffectiveRelocModel(const Triple &TT,
@ -143,7 +141,7 @@ public:
void addPreSched2() override;
void addPreRegAlloc() override;
};
}
} // namespace
TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) {
return new RISCVPassConfig(*this, PM);

2
llvm/lib/Target/RISCV/RISCVTargetMachine.h
View File

@ -47,6 +47,6 @@ public:
virtual bool isNoopAddrSpaceCast(unsigned SrcAS,
unsigned DstAS) const override;
};
}
} // namespace llvm
#endif