forked from OSchip/llvm-project
[ARM] Attempt to use whole register vmovs for MVE shuffles.
MVE doesn't have the range of shuffle instructions available in Neon. We also cannot use the trick of cutting a difficult vector shuffle in half to simplify things. Instead we need to be more careful about how we lower shuffles. This patch adds an extra combine that attempts to find "whole lane" vmovs when lowering shuffles of smaller types. This helps us make some shuffles a lot simpler, generating single lane movs for the parts that can make use of it, falling back to the original shuffle for the rest. Differential Revision: https://reviews.llvm.org/D69509
This commit is contained in:
David Green
parent
3a6eb5f160
commit
792fab343b
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@ -7809,6 +7809,92 @@ static SDValue LowerVECTOR_SHUFFLE_i1(SDValue Op, SelectionDAG &DAG,
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DAG.getConstant(ARMCC::NE, dl, MVT::i32));
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}
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static SDValue LowerVECTOR_SHUFFLEUsingMovs(SDValue Op,
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ArrayRef<int> ShuffleMask,
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SelectionDAG &DAG) {
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// Attempt to lower the vector shuffle using as many whole register movs as
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// possible. This is useful for types smaller than 32bits, which would
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// often otherwise become a series for grp movs.
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SDLoc dl(Op);
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EVT VT = Op.getValueType();
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if (VT.getScalarSizeInBits() >= 32)
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return SDValue();
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assert((VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v16i8) &&
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"Unexpected vector type");
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int NumElts = VT.getVectorNumElements();
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int QuarterSize = NumElts / 4;
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// The four final parts of the vector, as i32's
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SDValue Parts[4];
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// Look for full lane vmovs like <0,1,2,3> or <u,5,6,7> etc, (but not
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// <u,u,u,u>), returning the vmov lane index
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auto getMovIdx = [](ArrayRef<int> ShuffleMask, int Start, int Length) {
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// Detect which mov lane this would be from the first non-undef element.
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int MovIdx = -1;
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for (int i = 0; i < Length; i++) {
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if (ShuffleMask[Start + i] >= 0) {
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if (ShuffleMask[Start + i] % Length != i)
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return -1;
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MovIdx = ShuffleMask[Start + i] / Length;
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break;
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}
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}
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// If all items are undef, leave this for other combines
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if (MovIdx == -1)
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return -1;
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// Check the remaining values are the correct part of the same mov
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for (int i = 1; i < Length; i++) {
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if (ShuffleMask[Start + i] >= 0 &&
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(ShuffleMask[Start + i] / Length != MovIdx ||
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ShuffleMask[Start + i] % Length != i))
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return -1;
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}
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return MovIdx;
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};
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for (int Part = 0; Part < 4; ++Part) {
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// Does this part look like a mov
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int Elt = getMovIdx(ShuffleMask, Part * QuarterSize, QuarterSize);
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if (Elt != -1) {
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SDValue Input = Op->getOperand(0);
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if (Elt >= 4) {
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Input = Op->getOperand(1);
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Elt -= 4;
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}
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SDValue BitCast = DAG.getBitcast(MVT::v4i32, Input);
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Parts[Part] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, BitCast,
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DAG.getConstant(Elt, dl, MVT::i32));
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}
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}
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// Nothing interesting found, just return
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if (!Parts[0] && !Parts[1] && !Parts[2] && !Parts[3])
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return SDValue();
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// The other parts need to be built with the old shuffle vector, cast to a
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// v4i32 and extract_vector_elts
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if (!Parts[0] || !Parts[1] || !Parts[2] || !Parts[3]) {
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SmallVector<int, 16> NewShuffleMask;
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for (int Part = 0; Part < 4; ++Part)
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for (int i = 0; i < QuarterSize; i++)
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NewShuffleMask.push_back(
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Parts[Part] ? -1 : ShuffleMask[Part * QuarterSize + i]);
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SDValue NewShuffle = DAG.getVectorShuffle(
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VT, dl, Op->getOperand(0), Op->getOperand(1), NewShuffleMask);
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SDValue BitCast = DAG.getBitcast(MVT::v4i32, NewShuffle);
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for (int Part = 0; Part < 4; ++Part)
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if (!Parts[Part])
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Parts[Part] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
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BitCast, DAG.getConstant(Part, dl, MVT::i32));
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}
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// Build a vector out of the various parts and bitcast it back to the original
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// type.
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SDValue NewVec = DAG.getBuildVector(MVT::v4i32, dl, Parts);
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return DAG.getBitcast(VT, NewVec);
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}
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static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG,
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const ARMSubtarget *ST) {
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SDValue V1 = Op.getOperand(0);
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@ -8003,6 +8089,10 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG,
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if (SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG))
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return NewOp;
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if (ST->hasMVEIntegerOps())
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if (SDValue NewOp = LowerVECTOR_SHUFFLEUsingMovs(Op, ShuffleMask, DAG))
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return NewOp;
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return SDValue();
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}
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@ -260,9 +260,8 @@ define <8 x i16> @shuffle4_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) {
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; CHECK-NEXT: vpsel q0, q1, q0
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; CHECK-NEXT: vmov.u16 r0, q0[0]
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; CHECK-NEXT: vdup.16 q1, r0
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; CHECK-NEXT: vmov.u16 r0, q0[1]
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; CHECK-NEXT: vmov.16 q1[7], r0
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; CHECK-NEXT: add r0, sp, #16
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; CHECK-NEXT: vmov.f32 s7, s0
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; CHECK-NEXT: vldrw.u32 q0, [r0]
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; CHECK-NEXT: mov r0, sp
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; CHECK-NEXT: vcmp.i16 ne, q1, zr
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@ -98,11 +98,7 @@ define arm_aapcs_vfpcc <8 x i16> @shuffle3_i16(<8 x i16> %src) {
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; CHECK-LABEL: shuffle3_i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov q1, q0
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; CHECK-NEXT: vmov.u16 r0, q0[4]
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; CHECK-NEXT: vmov.16 q0[0], r0
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; CHECK-NEXT: vmov.u16 r0, q1[5]
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; CHECK-NEXT: vmov.16 q0[1], r0
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; CHECK-NEXT: vmov.u16 r0, q1[7]
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; CHECK-NEXT: vmov.u16 r0, q0[7]
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; CHECK-NEXT: vmov.16 q0[2], r0
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; CHECK-NEXT: vmov.u16 r0, q1[6]
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; CHECK-NEXT: vmov.16 q0[3], r0
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@ -114,6 +110,7 @@ define arm_aapcs_vfpcc <8 x i16> @shuffle3_i16(<8 x i16> %src) {
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; CHECK-NEXT: vmov.16 q0[6], r0
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; CHECK-NEXT: vmov.u16 r0, q1[0]
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; CHECK-NEXT: vmov.16 q0[7], r0
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; CHECK-NEXT: vmov.f32 s0, s6
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; CHECK-NEXT: bx lr
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entry:
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%out = shufflevector <8 x i16> %src, <8 x i16> undef, <8 x i32> <i32 4, i32 5, i32 7, i32 6, i32 3, i32 1, i32 2, i32 0>
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@ -387,16 +384,11 @@ entry:
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define arm_aapcs_vfpcc <8 x half> @shuffle3_f16(<8 x half> %src) {
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; CHECK-LABEL: shuffle3_f16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovx.f16 s4, s2
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; CHECK-NEXT: vmov r1, s2
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; CHECK-NEXT: vmov r0, s4
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; CHECK-NEXT: vmov.16 q1[0], r1
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; CHECK-NEXT: vmovx.f16 s8, s3
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; CHECK-NEXT: vmov.16 q1[1], r0
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; CHECK-NEXT: vmov r0, s8
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; CHECK-NEXT: vmovx.f16 s8, s1
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; CHECK-NEXT: vmov.16 q1[2], r0
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; CHECK-NEXT: vmovx.f16 s4, s3
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; CHECK-NEXT: vmov r0, s3
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; CHECK-NEXT: vmov r1, s4
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; CHECK-NEXT: vmovx.f16 s8, s1
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; CHECK-NEXT: vmov.16 q1[2], r1
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; CHECK-NEXT: vmov.16 q1[3], r0
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; CHECK-NEXT: vmov r0, s8
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; CHECK-NEXT: vmovx.f16 s8, s0
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@ -407,6 +399,7 @@ define arm_aapcs_vfpcc <8 x half> @shuffle3_f16(<8 x half> %src) {
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; CHECK-NEXT: vmov.16 q1[6], r0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: vmov.16 q1[7], r0
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; CHECK-NEXT: vmov.f32 s4, s2
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; CHECK-NEXT: vmov q0, q1
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; CHECK-NEXT: bx lr
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entry:
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@ -7,23 +7,11 @@
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define arm_aapcs_vfpcc <8 x i16> @shuffle_i16_45670123(<8 x i16> %s1, <8 x i16> %s2) {
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; CHECK-LABEL: shuffle_i16_45670123:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov q1, q0
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; CHECK-NEXT: vmov.u16 r0, q0[4]
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; CHECK-NEXT: vmov.16 q0[0], r0
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; CHECK-NEXT: vmov.u16 r0, q1[5]
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; CHECK-NEXT: vmov.16 q0[1], r0
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; CHECK-NEXT: vmov.u16 r0, q1[6]
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; CHECK-NEXT: vmov.16 q0[2], r0
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; CHECK-NEXT: vmov.u16 r0, q1[7]
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; CHECK-NEXT: vmov.16 q0[3], r0
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; CHECK-NEXT: vmov.u16 r0, q1[0]
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; CHECK-NEXT: vmov.16 q0[4], r0
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; CHECK-NEXT: vmov.u16 r0, q1[1]
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; CHECK-NEXT: vmov.16 q0[5], r0
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; CHECK-NEXT: vmov.u16 r0, q1[2]
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; CHECK-NEXT: vmov.16 q0[6], r0
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; CHECK-NEXT: vmov.u16 r0, q1[3]
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; CHECK-NEXT: vmov.16 q0[7], r0
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; CHECK-NEXT: vmov.f32 s4, s2
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; CHECK-NEXT: vmov.f32 s5, s3
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; CHECK-NEXT: vmov.f32 s6, s0
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; CHECK-NEXT: vmov.f32 s7, s1
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; CHECK-NEXT: vmov q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%out = shufflevector <8 x i16> %s1, <8 x i16> %s2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
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@ -33,23 +21,11 @@ entry:
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define arm_aapcs_vfpcc <8 x i16> @shuffle_i16_67452301(<8 x i16> %s1, <8 x i16> %s2) {
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; CHECK-LABEL: shuffle_i16_67452301:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov q1, q0
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; CHECK-NEXT: vmov.u16 r0, q0[6]
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; CHECK-NEXT: vmov.16 q0[0], r0
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; CHECK-NEXT: vmov.u16 r0, q1[7]
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; CHECK-NEXT: vmov.16 q0[1], r0
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; CHECK-NEXT: vmov.u16 r0, q1[4]
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; CHECK-NEXT: vmov.16 q0[2], r0
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; CHECK-NEXT: vmov.u16 r0, q1[5]
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; CHECK-NEXT: vmov.16 q0[3], r0
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; CHECK-NEXT: vmov.u16 r0, q1[2]
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; CHECK-NEXT: vmov.16 q0[4], r0
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; CHECK-NEXT: vmov.u16 r0, q1[3]
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; CHECK-NEXT: vmov.16 q0[5], r0
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; CHECK-NEXT: vmov.u16 r0, q1[0]
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; CHECK-NEXT: vmov.16 q0[6], r0
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; CHECK-NEXT: vmov.u16 r0, q1[1]
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; CHECK-NEXT: vmov.16 q0[7], r0
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; CHECK-NEXT: vmov.f32 s4, s3
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; CHECK-NEXT: vmov.f32 s5, s2
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; CHECK-NEXT: vmov.f32 s6, s1
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; CHECK-NEXT: vmov.f32 s7, s0
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; CHECK-NEXT: vmov q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%out = shufflevector <8 x i16> %s1, <8 x i16> %s2, <8 x i32> <i32 6, i32 7, i32 4, i32 5, i32 2, i32 3, i32 0, i32 1>
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@ -94,23 +70,8 @@ entry:
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define arm_aapcs_vfpcc <8 x i16> @shuffle_i16_0123cdef(<8 x i16> %s1, <8 x i16> %s2) {
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; CHECK-LABEL: shuffle_i16_0123cdef:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov q2, q0
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; CHECK-NEXT: vmov.u16 r0, q0[0]
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; CHECK-NEXT: vmov.16 q0[0], r0
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; CHECK-NEXT: vmov.u16 r0, q2[1]
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; CHECK-NEXT: vmov.16 q0[1], r0
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; CHECK-NEXT: vmov.u16 r0, q2[2]
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; CHECK-NEXT: vmov.16 q0[2], r0
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; CHECK-NEXT: vmov.u16 r0, q2[3]
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; CHECK-NEXT: vmov.16 q0[3], r0
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; CHECK-NEXT: vmov.u16 r0, q1[4]
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; CHECK-NEXT: vmov.16 q0[4], r0
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; CHECK-NEXT: vmov.u16 r0, q1[5]
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; CHECK-NEXT: vmov.16 q0[5], r0
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; CHECK-NEXT: vmov.u16 r0, q1[6]
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; CHECK-NEXT: vmov.16 q0[6], r0
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; CHECK-NEXT: vmov.u16 r0, q1[7]
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; CHECK-NEXT: vmov.16 q0[7], r0
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; CHECK-NEXT: vmov.f32 s2, s6
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; CHECK-NEXT: vmov.f32 s3, s7
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; CHECK-NEXT: bx lr
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entry:
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%out = shufflevector <8 x i16> %s1, <8 x i16> %s2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>
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@ -120,14 +81,10 @@ entry:
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define arm_aapcs_vfpcc <8 x i16> @shuffle_i16_u7u5u3u1(<8 x i16> %s1, <8 x i16> %s2) {
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; CHECK-LABEL: shuffle_i16_u7u5u3u1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.u16 r0, q0[7]
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; CHECK-NEXT: vmov.16 q1[1], r0
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; CHECK-NEXT: vmov.u16 r0, q0[5]
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; CHECK-NEXT: vmov.16 q1[3], r0
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; CHECK-NEXT: vmov.u16 r0, q0[3]
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; CHECK-NEXT: vmov.16 q1[5], r0
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; CHECK-NEXT: vmov.u16 r0, q0[1]
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; CHECK-NEXT: vmov.16 q1[7], r0
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; CHECK-NEXT: vmov.f32 s4, s3
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; CHECK-NEXT: vmov.f32 s5, s2
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; CHECK-NEXT: vmov.f32 s6, s1
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; CHECK-NEXT: vmov.f32 s7, s0
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; CHECK-NEXT: vmov q0, q1
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; CHECK-NEXT: bx lr
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entry:
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@ -138,14 +95,10 @@ entry:
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define arm_aapcs_vfpcc <8 x i16> @shuffle_i16_6u4u2u0u(<8 x i16> %s1, <8 x i16> %s2) {
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; CHECK-LABEL: shuffle_i16_6u4u2u0u:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.u16 r0, q0[6]
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; CHECK-NEXT: vmov.16 q1[0], r0
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; CHECK-NEXT: vmov.u16 r0, q0[4]
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; CHECK-NEXT: vmov.16 q1[2], r0
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; CHECK-NEXT: vmov.u16 r0, q0[2]
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; CHECK-NEXT: vmov.16 q1[4], r0
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; CHECK-NEXT: vmov.u16 r0, q0[0]
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; CHECK-NEXT: vmov.16 q1[6], r0
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; CHECK-NEXT: vmov.f32 s4, s3
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; CHECK-NEXT: vmov.f32 s5, s2
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; CHECK-NEXT: vmov.f32 s6, s1
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; CHECK-NEXT: vmov.f32 s7, s0
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; CHECK-NEXT: vmov q0, q1
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; CHECK-NEXT: bx lr
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entry:
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@ -179,39 +132,11 @@ entry:
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define arm_aapcs_vfpcc <16 x i8> @shuffle_i8_cdef89ab45670123(<16 x i8> %s1, <16 x i8> %s2) {
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; CHECK-LABEL: shuffle_i8_cdef89ab45670123:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov q1, q0
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; CHECK-NEXT: vmov.u8 r0, q0[12]
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; CHECK-NEXT: vmov.8 q0[0], r0
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; CHECK-NEXT: vmov.u8 r0, q1[13]
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; CHECK-NEXT: vmov.8 q0[1], r0
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; CHECK-NEXT: vmov.u8 r0, q1[14]
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; CHECK-NEXT: vmov.8 q0[2], r0
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; CHECK-NEXT: vmov.u8 r0, q1[15]
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; CHECK-NEXT: vmov.8 q0[3], r0
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; CHECK-NEXT: vmov.u8 r0, q1[8]
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; CHECK-NEXT: vmov.8 q0[4], r0
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; CHECK-NEXT: vmov.u8 r0, q1[9]
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; CHECK-NEXT: vmov.8 q0[5], r0
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; CHECK-NEXT: vmov.u8 r0, q1[10]
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; CHECK-NEXT: vmov.8 q0[6], r0
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; CHECK-NEXT: vmov.u8 r0, q1[11]
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; CHECK-NEXT: vmov.8 q0[7], r0
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; CHECK-NEXT: vmov.u8 r0, q1[4]
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; CHECK-NEXT: vmov.8 q0[8], r0
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; CHECK-NEXT: vmov.u8 r0, q1[5]
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; CHECK-NEXT: vmov.8 q0[9], r0
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; CHECK-NEXT: vmov.u8 r0, q1[6]
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; CHECK-NEXT: vmov.8 q0[10], r0
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; CHECK-NEXT: vmov.u8 r0, q1[7]
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; CHECK-NEXT: vmov.8 q0[11], r0
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; CHECK-NEXT: vmov.u8 r0, q1[0]
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; CHECK-NEXT: vmov.8 q0[12], r0
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; CHECK-NEXT: vmov.u8 r0, q1[1]
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; CHECK-NEXT: vmov.8 q0[13], r0
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; CHECK-NEXT: vmov.u8 r0, q1[2]
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; CHECK-NEXT: vmov.8 q0[14], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[3]
|
||||
; CHECK-NEXT: vmov.8 q0[15], r0
|
||||
; CHECK-NEXT: vmov.f32 s4, s3
|
||||
; CHECK-NEXT: vmov.f32 s5, s2
|
||||
; CHECK-NEXT: vmov.f32 s6, s1
|
||||
; CHECK-NEXT: vmov.f32 s7, s0
|
||||
; CHECK-NEXT: vmov q0, q1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%out = shufflevector <16 x i8> %s1, <16 x i8> %s2, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
|
||||
|
|
@ -314,39 +239,11 @@ entry:
|
|||
define arm_aapcs_vfpcc <16 x i8> @shuffle_i8_0123ghij4567klmn(<16 x i8> %s1, <16 x i8> %s2) {
|
||||
; CHECK-LABEL: shuffle_i8_0123ghij4567klmn:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmov q2, q0
|
||||
; CHECK-NEXT: vmov.u8 r0, q0[0]
|
||||
; CHECK-NEXT: vmov.8 q0[0], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[1]
|
||||
; CHECK-NEXT: vmov.8 q0[1], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[2]
|
||||
; CHECK-NEXT: vmov.8 q0[2], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[3]
|
||||
; CHECK-NEXT: vmov.8 q0[3], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[0]
|
||||
; CHECK-NEXT: vmov.8 q0[4], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[1]
|
||||
; CHECK-NEXT: vmov.8 q0[5], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[2]
|
||||
; CHECK-NEXT: vmov.8 q0[6], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[3]
|
||||
; CHECK-NEXT: vmov.8 q0[7], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[4]
|
||||
; CHECK-NEXT: vmov.8 q0[8], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[5]
|
||||
; CHECK-NEXT: vmov.8 q0[9], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[6]
|
||||
; CHECK-NEXT: vmov.8 q0[10], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[7]
|
||||
; CHECK-NEXT: vmov.8 q0[11], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[4]
|
||||
; CHECK-NEXT: vmov.8 q0[12], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[5]
|
||||
; CHECK-NEXT: vmov.8 q0[13], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[6]
|
||||
; CHECK-NEXT: vmov.8 q0[14], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[7]
|
||||
; CHECK-NEXT: vmov.8 q0[15], r0
|
||||
; CHECK-NEXT: vmov.f32 s8, s0
|
||||
; CHECK-NEXT: vmov.f32 s9, s4
|
||||
; CHECK-NEXT: vmov.f32 s10, s1
|
||||
; CHECK-NEXT: vmov.f32 s11, s5
|
||||
; CHECK-NEXT: vmov q0, q2
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%out = shufflevector <16 x i8> %s1, <16 x i8> %s2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 16, i32 17, i32 18, i32 19, i32 4, i32 5, i32 6, i32 7, i32 20, i32 21, i32 22, i32 23>
|
||||
|
|
@ -356,31 +253,11 @@ entry:
|
|||
define arm_aapcs_vfpcc <16 x i8> @shuffle_i8_cdeu89ub4u67u123(<16 x i8> %s1, <16 x i8> %s2) {
|
||||
; CHECK-LABEL: shuffle_i8_cdeu89ub4u67u123:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmov q1, q0
|
||||
; CHECK-NEXT: vmov.u8 r0, q0[12]
|
||||
; CHECK-NEXT: vmov.8 q0[0], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[13]
|
||||
; CHECK-NEXT: vmov.8 q0[1], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[14]
|
||||
; CHECK-NEXT: vmov.8 q0[2], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[8]
|
||||
; CHECK-NEXT: vmov.8 q0[4], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[9]
|
||||
; CHECK-NEXT: vmov.8 q0[5], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[11]
|
||||
; CHECK-NEXT: vmov.8 q0[7], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[4]
|
||||
; CHECK-NEXT: vmov.8 q0[8], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[6]
|
||||
; CHECK-NEXT: vmov.8 q0[10], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[7]
|
||||
; CHECK-NEXT: vmov.8 q0[11], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[1]
|
||||
; CHECK-NEXT: vmov.8 q0[13], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[2]
|
||||
; CHECK-NEXT: vmov.8 q0[14], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[3]
|
||||
; CHECK-NEXT: vmov.8 q0[15], r0
|
||||
; CHECK-NEXT: vmov.f32 s4, s3
|
||||
; CHECK-NEXT: vmov.f32 s5, s2
|
||||
; CHECK-NEXT: vmov.f32 s6, s1
|
||||
; CHECK-NEXT: vmov.f32 s7, s0
|
||||
; CHECK-NEXT: vmov q0, q1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%out = shufflevector <16 x i8> %s1, <16 x i8> %s2, <16 x i32> <i32 12, i32 13, i32 14, i32 undef, i32 8, i32 9, i32 undef, i32 11, i32 4, i32 undef, i32 6, i32 7, i32 undef, i32 1, i32 2, i32 3>
|
||||
|
|
@ -390,23 +267,11 @@ entry:
|
|||
define arm_aapcs_vfpcc <16 x i8> @shuffle_i8_cduu8uubuu67u12u(<16 x i8> %s1, <16 x i8> %s2) {
|
||||
; CHECK-LABEL: shuffle_i8_cduu8uubuu67u12u:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmov q1, q0
|
||||
; CHECK-NEXT: vmov.u8 r0, q0[12]
|
||||
; CHECK-NEXT: vmov.8 q0[0], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[13]
|
||||
; CHECK-NEXT: vmov.8 q0[1], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[8]
|
||||
; CHECK-NEXT: vmov.8 q0[4], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[11]
|
||||
; CHECK-NEXT: vmov.8 q0[7], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[6]
|
||||
; CHECK-NEXT: vmov.8 q0[10], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[7]
|
||||
; CHECK-NEXT: vmov.8 q0[11], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[1]
|
||||
; CHECK-NEXT: vmov.8 q0[13], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[2]
|
||||
; CHECK-NEXT: vmov.8 q0[14], r0
|
||||
; CHECK-NEXT: vmov.f32 s4, s3
|
||||
; CHECK-NEXT: vmov.f32 s5, s2
|
||||
; CHECK-NEXT: vmov.f32 s6, s1
|
||||
; CHECK-NEXT: vmov.f32 s7, s0
|
||||
; CHECK-NEXT: vmov q0, q1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%out = shufflevector <16 x i8> %s1, <16 x i8> %s2, <16 x i32> <i32 12, i32 13, i32 undef, i32 undef, i32 8, i32 undef, i32 undef, i32 11, i32 undef, i32 undef, i32 6, i32 7, i32 undef, i32 1, i32 2, i32 undef>
|
||||
|
|
@ -416,14 +281,10 @@ entry:
|
|||
define arm_aapcs_vfpcc <16 x i8> @shuffle_i8_cuuuuuubuu6uuu2u(<16 x i8> %s1, <16 x i8> %s2) {
|
||||
; CHECK-LABEL: shuffle_i8_cuuuuuubuu6uuu2u:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmov.u8 r0, q0[12]
|
||||
; CHECK-NEXT: vmov.8 q1[0], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q0[11]
|
||||
; CHECK-NEXT: vmov.8 q1[7], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q0[6]
|
||||
; CHECK-NEXT: vmov.8 q1[10], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q0[2]
|
||||
; CHECK-NEXT: vmov.8 q1[14], r0
|
||||
; CHECK-NEXT: vmov.f32 s4, s3
|
||||
; CHECK-NEXT: vmov.f32 s5, s2
|
||||
; CHECK-NEXT: vmov.f32 s6, s1
|
||||
; CHECK-NEXT: vmov.f32 s7, s0
|
||||
; CHECK-NEXT: vmov q0, q1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
|
|
@ -434,36 +295,16 @@ entry:
|
|||
define arm_aapcs_vfpcc <16 x i8> @shuffle_i8_cdef89ab45u700123(<16 x i8> %s1, <16 x i8> %s2) {
|
||||
; CHECK-LABEL: shuffle_i8_cdef89ab45u700123:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmov q1, q0
|
||||
; CHECK-NEXT: vmov.u8 r0, q0[12]
|
||||
; CHECK-NEXT: vmov.8 q0[0], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[13]
|
||||
; CHECK-NEXT: vmov.8 q0[1], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[14]
|
||||
; CHECK-NEXT: vmov.8 q0[2], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[15]
|
||||
; CHECK-NEXT: vmov.8 q0[3], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[8]
|
||||
; CHECK-NEXT: vmov.8 q0[4], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[9]
|
||||
; CHECK-NEXT: vmov.8 q0[5], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[10]
|
||||
; CHECK-NEXT: vmov.8 q0[6], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[11]
|
||||
; CHECK-NEXT: vmov.8 q0[7], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[4]
|
||||
; CHECK-NEXT: vmov.8 q0[8], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[5]
|
||||
; CHECK-NEXT: vmov.8 q0[9], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[0]
|
||||
; CHECK-NEXT: vmov.8 q0[11], r0
|
||||
; CHECK-NEXT: vmov.8 q0[12], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[1]
|
||||
; CHECK-NEXT: vmov.8 q0[13], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[2]
|
||||
; CHECK-NEXT: vmov.8 q0[14], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[3]
|
||||
; CHECK-NEXT: vmov.8 q0[15], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q0[4]
|
||||
; CHECK-NEXT: vmov.8 q1[8], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q0[5]
|
||||
; CHECK-NEXT: vmov.8 q1[9], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q0[0]
|
||||
; CHECK-NEXT: vmov.8 q1[11], r0
|
||||
; CHECK-NEXT: vmov.f32 s4, s3
|
||||
; CHECK-NEXT: vmov.f32 s5, s2
|
||||
; CHECK-NEXT: vmov.f32 s7, s0
|
||||
; CHECK-NEXT: vmov q0, q1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%out = shufflevector <16 x i8> %s1, <16 x i8> %s2, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 undef, i32 0, i32 0, i32 1, i32 2, i32 3>
|
||||
|
|
@ -477,26 +318,10 @@ entry:
|
|||
define arm_aapcs_vfpcc <8 x half> @shuffle_f16_45670123(<8 x half> %s1, <8 x half> %s2) {
|
||||
; CHECK-LABEL: shuffle_f16_45670123:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmovx.f16 s4, s2
|
||||
; CHECK-NEXT: vmov r1, s2
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmov.16 q1[0], r1
|
||||
; CHECK-NEXT: vmov.16 q1[1], r0
|
||||
; CHECK-NEXT: vmov r0, s3
|
||||
; CHECK-NEXT: vmovx.f16 s8, s3
|
||||
; CHECK-NEXT: vmov.16 q1[2], r0
|
||||
; CHECK-NEXT: vmov r0, s8
|
||||
; CHECK-NEXT: vmovx.f16 s8, s0
|
||||
; CHECK-NEXT: vmov.16 q1[3], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmov.16 q1[4], r0
|
||||
; CHECK-NEXT: vmov r0, s8
|
||||
; CHECK-NEXT: vmov.16 q1[5], r0
|
||||
; CHECK-NEXT: vmov r0, s1
|
||||
; CHECK-NEXT: vmovx.f16 s0, s1
|
||||
; CHECK-NEXT: vmov.16 q1[6], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmov.16 q1[7], r0
|
||||
; CHECK-NEXT: vmov.f32 s4, s2
|
||||
; CHECK-NEXT: vmov.f32 s5, s3
|
||||
; CHECK-NEXT: vmov.f32 s6, s0
|
||||
; CHECK-NEXT: vmov.f32 s7, s1
|
||||
; CHECK-NEXT: vmov q0, q1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
|
|
@ -507,26 +332,10 @@ entry:
|
|||
define arm_aapcs_vfpcc <8 x half> @shuffle_f16_67452301(<8 x half> %s1, <8 x half> %s2) {
|
||||
; CHECK-LABEL: shuffle_f16_67452301:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmovx.f16 s4, s3
|
||||
; CHECK-NEXT: vmov r1, s3
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmov.16 q1[0], r1
|
||||
; CHECK-NEXT: vmov.16 q1[1], r0
|
||||
; CHECK-NEXT: vmov r0, s2
|
||||
; CHECK-NEXT: vmovx.f16 s8, s2
|
||||
; CHECK-NEXT: vmov.16 q1[2], r0
|
||||
; CHECK-NEXT: vmov r0, s8
|
||||
; CHECK-NEXT: vmovx.f16 s8, s1
|
||||
; CHECK-NEXT: vmov.16 q1[3], r0
|
||||
; CHECK-NEXT: vmov r0, s1
|
||||
; CHECK-NEXT: vmov.16 q1[4], r0
|
||||
; CHECK-NEXT: vmov r0, s8
|
||||
; CHECK-NEXT: vmov.16 q1[5], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmovx.f16 s0, s0
|
||||
; CHECK-NEXT: vmov.16 q1[6], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmov.16 q1[7], r0
|
||||
; CHECK-NEXT: vmov.f32 s4, s3
|
||||
; CHECK-NEXT: vmov.f32 s5, s2
|
||||
; CHECK-NEXT: vmov.f32 s6, s1
|
||||
; CHECK-NEXT: vmov.f32 s7, s0
|
||||
; CHECK-NEXT: vmov q0, q1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
|
|
@ -576,27 +385,8 @@ entry:
|
|||
define arm_aapcs_vfpcc <8 x half> @shuffle_f16_0123cdef(<8 x half> %s1, <8 x half> %s2) {
|
||||
; CHECK-LABEL: shuffle_f16_0123cdef:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmov q2, q0
|
||||
; CHECK-NEXT: vmovx.f16 s4, s7
|
||||
; CHECK-NEXT: vmovx.f16 s0, s8
|
||||
; CHECK-NEXT: vmov r1, s8
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmov.16 q0[0], r1
|
||||
; CHECK-NEXT: vmov.16 q0[1], r0
|
||||
; CHECK-NEXT: vmov r0, s9
|
||||
; CHECK-NEXT: vmovx.f16 s8, s9
|
||||
; CHECK-NEXT: vmov.16 q0[2], r0
|
||||
; CHECK-NEXT: vmov r0, s8
|
||||
; CHECK-NEXT: vmovx.f16 s8, s6
|
||||
; CHECK-NEXT: vmov.16 q0[3], r0
|
||||
; CHECK-NEXT: vmov r0, s6
|
||||
; CHECK-NEXT: vmov.16 q0[4], r0
|
||||
; CHECK-NEXT: vmov r0, s8
|
||||
; CHECK-NEXT: vmov.16 q0[5], r0
|
||||
; CHECK-NEXT: vmov r0, s7
|
||||
; CHECK-NEXT: vmov.16 q0[6], r0
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmov.16 q0[7], r0
|
||||
; CHECK-NEXT: vmov.f32 s2, s6
|
||||
; CHECK-NEXT: vmov.f32 s3, s7
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%out = shufflevector <8 x half> %s1, <8 x half> %s2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>
|
||||
|
|
@ -606,18 +396,10 @@ entry:
|
|||
define arm_aapcs_vfpcc <8 x half> @shuffle_f16_u7u5u3u1(<8 x half> %s1, <8 x half> %s2) {
|
||||
; CHECK-LABEL: shuffle_f16_u7u5u3u1:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmovx.f16 s4, s3
|
||||
; CHECK-NEXT: vmovx.f16 s8, s1
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmovx.f16 s4, s2
|
||||
; CHECK-NEXT: vmov r1, s4
|
||||
; CHECK-NEXT: vmov.16 q1[1], r0
|
||||
; CHECK-NEXT: vmov.16 q1[3], r1
|
||||
; CHECK-NEXT: vmov r0, s8
|
||||
; CHECK-NEXT: vmovx.f16 s0, s0
|
||||
; CHECK-NEXT: vmov.16 q1[5], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmov.16 q1[7], r0
|
||||
; CHECK-NEXT: vmov.f32 s4, s3
|
||||
; CHECK-NEXT: vmov.f32 s5, s2
|
||||
; CHECK-NEXT: vmov.f32 s6, s1
|
||||
; CHECK-NEXT: vmov.f32 s7, s0
|
||||
; CHECK-NEXT: vmov q0, q1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
|
|
@ -628,14 +410,10 @@ entry:
|
|||
define arm_aapcs_vfpcc <8 x half> @shuffle_f16_6u4u2u0u(<8 x half> %s1, <8 x half> %s2) {
|
||||
; CHECK-LABEL: shuffle_f16_6u4u2u0u:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmov r0, s3
|
||||
; CHECK-NEXT: vmov.16 q1[0], r0
|
||||
; CHECK-NEXT: vmov r1, s2
|
||||
; CHECK-NEXT: vmov.16 q1[2], r1
|
||||
; CHECK-NEXT: vmov r0, s1
|
||||
; CHECK-NEXT: vmov.16 q1[4], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmov.16 q1[6], r0
|
||||
; CHECK-NEXT: vmov.f32 s4, s3
|
||||
; CHECK-NEXT: vmov.f32 s5, s2
|
||||
; CHECK-NEXT: vmov.f32 s6, s1
|
||||
; CHECK-NEXT: vmov.f32 s7, s0
|
||||
; CHECK-NEXT: vmov q0, q1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -8,8 +8,8 @@ define void @vldst4(half* nocapture readonly %pIn, half* nocapture %pOut, i32 %n
|
|||
; CHECK-NEXT: push {r7, lr}
|
||||
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
|
||||
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
|
||||
; CHECK-NEXT: .pad #40
|
||||
; CHECK-NEXT: sub sp, #40
|
||||
; CHECK-NEXT: .pad #104
|
||||
; CHECK-NEXT: sub sp, #104
|
||||
; CHECK-NEXT: muls r2, r3, r2
|
||||
; CHECK-NEXT: movs r3, #0
|
||||
; CHECK-NEXT: cmp.w r3, r2, lsr #2
|
||||
|
|
@ -17,7 +17,7 @@ define void @vldst4(half* nocapture readonly %pIn, half* nocapture %pOut, i32 %n
|
|||
; CHECK-NEXT: @ %bb.1: @ %vector.ph
|
||||
; CHECK-NEXT: mvn r3, #7
|
||||
; CHECK-NEXT: and.w r2, r3, r2, lsr #2
|
||||
; CHECK-NEXT: vldr.16 s0, [sp, #112]
|
||||
; CHECK-NEXT: vldr.16 s0, [sp, #176]
|
||||
; CHECK-NEXT: subs r2, #8
|
||||
; CHECK-NEXT: movs r3, #1
|
||||
; CHECK-NEXT: sub.w r12, r0, #64
|
||||
|
|
@ -25,192 +25,214 @@ define void @vldst4(half* nocapture readonly %pIn, half* nocapture %pOut, i32 %n
|
|||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: vdup.16 q0, r2
|
||||
; CHECK-NEXT: subs r1, #64
|
||||
; CHECK-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill
|
||||
; CHECK-NEXT: vstrw.32 q0, [sp, #80] @ 16-byte Spill
|
||||
; CHECK-NEXT: dls lr, lr
|
||||
; CHECK-NEXT: .LBB0_2: @ %vector.body
|
||||
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
|
||||
; CHECK-NEXT: vldrh.u16 q0, [r12, #64]!
|
||||
; CHECK-NEXT: vldrw.u32 q2, [sp, #16] @ 16-byte Reload
|
||||
; CHECK-NEXT: vmov r3, s0
|
||||
; CHECK-NEXT: vldrh.u16 q7, [r12, #16]
|
||||
; CHECK-NEXT: vmov r2, s2
|
||||
; CHECK-NEXT: vmov.16 q1[0], r3
|
||||
; CHECK-NEXT: vmov.16 q1[1], r2
|
||||
; CHECK-NEXT: vmov r2, s28
|
||||
; CHECK-NEXT: vldrh.u16 q6, [r12, #32]
|
||||
; CHECK-NEXT: vmov.16 q1[2], r2
|
||||
; CHECK-NEXT: vmov r2, s30
|
||||
; CHECK-NEXT: vldrh.u16 q5, [r12, #48]
|
||||
; CHECK-NEXT: vmov.16 q1[3], r2
|
||||
; CHECK-NEXT: vldrh.u16 q4, [r12, #48]
|
||||
; CHECK-NEXT: vldrh.u16 q7, [r12, #16]
|
||||
; CHECK-NEXT: vmov r2, s24
|
||||
; CHECK-NEXT: vmovx.f16 s12, s16
|
||||
; CHECK-NEXT: vmov.16 q1[4], r2
|
||||
; CHECK-NEXT: vmov r2, s26
|
||||
; CHECK-NEXT: vmov.16 q1[5], r2
|
||||
; CHECK-NEXT: vmov r2, s20
|
||||
; CHECK-NEXT: vmov r3, s26
|
||||
; CHECK-NEXT: vmov.16 q1[5], r3
|
||||
; CHECK-NEXT: vmov r2, s16
|
||||
; CHECK-NEXT: vmov.16 q1[6], r2
|
||||
; CHECK-NEXT: vmov r2, s22
|
||||
; CHECK-NEXT: vmov.16 q1[7], r2
|
||||
; CHECK-NEXT: vmov q4, q2
|
||||
; CHECK-NEXT: vmul.f16 q1, q1, q2
|
||||
; CHECK-NEXT: vmovx.f16 s8, s2
|
||||
; CHECK-NEXT: vmov r3, s8
|
||||
; CHECK-NEXT: vmovx.f16 s8, s0
|
||||
; CHECK-NEXT: vmov r0, s8
|
||||
; CHECK-NEXT: vmovx.f16 s12, s28
|
||||
; CHECK-NEXT: vmov.16 q2[0], r0
|
||||
; CHECK-NEXT: vmov r0, s12
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: vmov.16 q2[0], r2
|
||||
; CHECK-NEXT: vmov r3, s2
|
||||
; CHECK-NEXT: vmov.16 q2[1], r3
|
||||
; CHECK-NEXT: vmovx.f16 s12, s30
|
||||
; CHECK-NEXT: vmov.16 q2[2], r0
|
||||
; CHECK-NEXT: vmov r0, s12
|
||||
; CHECK-NEXT: vmovx.f16 s12, s24
|
||||
; CHECK-NEXT: vmov.16 q2[3], r0
|
||||
; CHECK-NEXT: vmov r0, s12
|
||||
; CHECK-NEXT: vmovx.f16 s12, s26
|
||||
; CHECK-NEXT: vmov.16 q2[4], r0
|
||||
; CHECK-NEXT: vmov r0, s12
|
||||
; CHECK-NEXT: vmovx.f16 s12, s20
|
||||
; CHECK-NEXT: vmov r2, s28
|
||||
; CHECK-NEXT: vmov.16 q2[2], r2
|
||||
; CHECK-NEXT: vmov r2, s18
|
||||
; CHECK-NEXT: vmov.16 q1[7], r2
|
||||
; CHECK-NEXT: vmov r2, s30
|
||||
; CHECK-NEXT: vmov.16 q2[3], r2
|
||||
; CHECK-NEXT: vmov.f32 s10, s6
|
||||
; CHECK-NEXT: vmov.f32 s11, s7
|
||||
; CHECK-NEXT: vldrw.u32 q1, [sp, #80] @ 16-byte Reload
|
||||
; CHECK-NEXT: vmul.f16 q5, q2, q1
|
||||
; CHECK-NEXT: vmovx.f16 s4, s2
|
||||
; CHECK-NEXT: vmov r3, s4
|
||||
; CHECK-NEXT: vmovx.f16 s4, s0
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmovx.f16 s8, s28
|
||||
; CHECK-NEXT: vmov.16 q1[0], r0
|
||||
; CHECK-NEXT: vmov r0, s8
|
||||
; CHECK-NEXT: vmov.16 q1[1], r3
|
||||
; CHECK-NEXT: vmovx.f16 s8, s26
|
||||
; CHECK-NEXT: vmov.16 q1[2], r0
|
||||
; CHECK-NEXT: vmov r0, s8
|
||||
; CHECK-NEXT: vmovx.f16 s8, s24
|
||||
; CHECK-NEXT: vmov r2, s22
|
||||
; CHECK-NEXT: vmov r3, s8
|
||||
; CHECK-NEXT: vmovx.f16 s0, s1
|
||||
; CHECK-NEXT: vmov.16 q2[4], r3
|
||||
; CHECK-NEXT: vmov r3, s0
|
||||
; CHECK-NEXT: vmov.16 q2[5], r0
|
||||
; CHECK-NEXT: vmov r0, s12
|
||||
; CHECK-NEXT: vmovx.f16 s12, s22
|
||||
; CHECK-NEXT: vmovx.f16 s12, s18
|
||||
; CHECK-NEXT: vmov.16 q2[6], r0
|
||||
; CHECK-NEXT: vmov r0, s12
|
||||
; CHECK-NEXT: vmovx.f16 s12, s30
|
||||
; CHECK-NEXT: vmov.16 q2[7], r0
|
||||
; CHECK-NEXT: vmov r2, s4
|
||||
; CHECK-NEXT: vmul.f16 q2, q2, q4
|
||||
; CHECK-NEXT: vstrw.32 q1, [sp] @ 16-byte Spill
|
||||
; CHECK-NEXT: vmov q1, q4
|
||||
; CHECK-NEXT: vmov.16 q4[0], r2
|
||||
; CHECK-NEXT: vmov r0, s8
|
||||
; CHECK-NEXT: vmovx.f16 s0, s3
|
||||
; CHECK-NEXT: vmov.16 q4[1], r0
|
||||
; CHECK-NEXT: vmov r0, s1
|
||||
; CHECK-NEXT: vmov.16 q3[0], r0
|
||||
; CHECK-NEXT: vmov r2, s3
|
||||
; CHECK-NEXT: vmov.16 q3[1], r2
|
||||
; CHECK-NEXT: vmov r0, s29
|
||||
; CHECK-NEXT: vmov.16 q3[2], r0
|
||||
; CHECK-NEXT: vmov r0, s31
|
||||
; CHECK-NEXT: vmov.16 q3[3], r0
|
||||
; CHECK-NEXT: vmov r0, s25
|
||||
; CHECK-NEXT: vmov.16 q3[4], r0
|
||||
; CHECK-NEXT: vmov r0, s27
|
||||
; CHECK-NEXT: vmov.16 q3[5], r0
|
||||
; CHECK-NEXT: vmov r0, s21
|
||||
; CHECK-NEXT: vmov.16 q3[6], r0
|
||||
; CHECK-NEXT: vmov r0, s23
|
||||
; CHECK-NEXT: vmov.16 q3[7], r0
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: vmul.f16 q3, q3, q1
|
||||
; CHECK-NEXT: vmovx.f16 s4, s1
|
||||
; CHECK-NEXT: vmov r0, s12
|
||||
; CHECK-NEXT: vmov.16 q4[2], r0
|
||||
; CHECK-NEXT: vmov.16 q1[3], r0
|
||||
; CHECK-NEXT: vldrw.u32 q3, [sp, #80] @ 16-byte Reload
|
||||
; CHECK-NEXT: vmov.f32 s6, s10
|
||||
; CHECK-NEXT: vstrw.32 q5, [sp, #16] @ 16-byte Spill
|
||||
; CHECK-NEXT: vmov.f32 s7, s11
|
||||
; CHECK-NEXT: vmov.16 q2[0], r2
|
||||
; CHECK-NEXT: vmul.f16 q1, q1, q3
|
||||
; CHECK-NEXT: vmov r2, s27
|
||||
; CHECK-NEXT: vmov r0, s6
|
||||
; CHECK-NEXT: vstrw.32 q1, [sp, #32] @ 16-byte Spill
|
||||
; CHECK-NEXT: vmovx.f16 s4, s22
|
||||
; CHECK-NEXT: vmov.16 q2[1], r0
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmov.16 q0[0], r0
|
||||
; CHECK-NEXT: vmov.16 q2[4], r0
|
||||
; CHECK-NEXT: vmov r0, s25
|
||||
; CHECK-NEXT: vmov.16 q1[4], r0
|
||||
; CHECK-NEXT: vmov r0, s17
|
||||
; CHECK-NEXT: vmov.16 q1[5], r2
|
||||
; CHECK-NEXT: vmov r2, s1
|
||||
; CHECK-NEXT: vstrw.32 q2, [sp, #64] @ 16-byte Spill
|
||||
; CHECK-NEXT: vmov.16 q1[6], r0
|
||||
; CHECK-NEXT: vmov r0, s3
|
||||
; CHECK-NEXT: vmov.16 q2[0], r2
|
||||
; CHECK-NEXT: vmov.16 q2[1], r0
|
||||
; CHECK-NEXT: vmov r0, s29
|
||||
; CHECK-NEXT: vmov.16 q2[2], r0
|
||||
; CHECK-NEXT: vmov r0, s19
|
||||
; CHECK-NEXT: vmov.16 q1[7], r0
|
||||
; CHECK-NEXT: vmov r0, s31
|
||||
; CHECK-NEXT: vmov.16 q2[3], r0
|
||||
; CHECK-NEXT: vmov.f32 s10, s6
|
||||
; CHECK-NEXT: vmov.f32 s11, s7
|
||||
; CHECK-NEXT: vmovx.f16 s4, s3
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmov.16 q0[0], r3
|
||||
; CHECK-NEXT: vmovx.f16 s4, s29
|
||||
; CHECK-NEXT: vmov.16 q0[1], r2
|
||||
; CHECK-NEXT: vmov.16 q0[1], r0
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmovx.f16 s4, s31
|
||||
; CHECK-NEXT: vmovx.f16 s4, s27
|
||||
; CHECK-NEXT: vmov.16 q0[2], r0
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmovx.f16 s4, s25
|
||||
; CHECK-NEXT: vmul.f16 q5, q2, q3
|
||||
; CHECK-NEXT: vmov r3, s4
|
||||
; CHECK-NEXT: vmovx.f16 s8, s17
|
||||
; CHECK-NEXT: vmov.16 q1[4], r3
|
||||
; CHECK-NEXT: vmov r2, s23
|
||||
; CHECK-NEXT: vmov.16 q1[5], r0
|
||||
; CHECK-NEXT: vmov r0, s8
|
||||
; CHECK-NEXT: vmovx.f16 s8, s19
|
||||
; CHECK-NEXT: vmov.16 q1[6], r0
|
||||
; CHECK-NEXT: vmov r0, s8
|
||||
; CHECK-NEXT: vmovx.f16 s8, s31
|
||||
; CHECK-NEXT: vmov.16 q1[7], r0
|
||||
; CHECK-NEXT: vmov r0, s8
|
||||
; CHECK-NEXT: vmov.16 q0[3], r0
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmovx.f16 s4, s27
|
||||
; CHECK-NEXT: vmov.16 q0[4], r0
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmovx.f16 s4, s21
|
||||
; CHECK-NEXT: vmov.16 q0[5], r0
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmovx.f16 s4, s23
|
||||
; CHECK-NEXT: vmov.16 q0[6], r0
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vldrw.u32 q1, [sp, #16] @ 16-byte Reload
|
||||
; CHECK-NEXT: vmov.16 q0[7], r0
|
||||
; CHECK-NEXT: vldrw.u32 q6, [sp] @ 16-byte Reload
|
||||
; CHECK-NEXT: vmul.f16 q5, q0, q1
|
||||
; CHECK-NEXT: vmov r2, s10
|
||||
; CHECK-NEXT: vmov r0, s20
|
||||
; CHECK-NEXT: vmovx.f16 s0, s24
|
||||
; CHECK-NEXT: vmov.16 q4[3], r0
|
||||
; CHECK-NEXT: vldrw.u32 q2, [sp, #32] @ 16-byte Reload
|
||||
; CHECK-NEXT: vmov.f32 s2, s6
|
||||
; CHECK-NEXT: vmov.f32 s3, s7
|
||||
; CHECK-NEXT: vmov.16 q1[2], r2
|
||||
; CHECK-NEXT: vmul.f16 q6, q0, q3
|
||||
; CHECK-NEXT: vmovx.f16 s0, s23
|
||||
; CHECK-NEXT: vmov r0, s27
|
||||
; CHECK-NEXT: vmov.16 q1[3], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmovx.f16 s0, s8
|
||||
; CHECK-NEXT: vmovx.f16 s0, s27
|
||||
; CHECK-NEXT: vmov.16 q1[6], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmov.16 q1[7], r0
|
||||
; CHECK-NEXT: vmov r2, s11
|
||||
; CHECK-NEXT: vstrw.32 q1, [sp, #48] @ 16-byte Spill
|
||||
; CHECK-NEXT: vldrw.u32 q1, [sp, #16] @ 16-byte Reload
|
||||
; CHECK-NEXT: vmov r0, s7
|
||||
; CHECK-NEXT: vmovx.f16 s0, s7
|
||||
; CHECK-NEXT: vmov.16 q4[0], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmov.16 q4[1], r2
|
||||
; CHECK-NEXT: vmovx.f16 s0, s11
|
||||
; CHECK-NEXT: vmov.16 q4[4], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmovx.f16 s0, s12
|
||||
; CHECK-NEXT: vmov.16 q4[5], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmovx.f16 s0, s20
|
||||
; CHECK-NEXT: vmov.16 q4[6], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmovx.f16 s4, s26
|
||||
; CHECK-NEXT: vmov.16 q4[7], r0
|
||||
; CHECK-NEXT: vmov r0, s26
|
||||
; CHECK-NEXT: vmov.16 q0[0], r0
|
||||
; CHECK-NEXT: vmov r0, s14
|
||||
; CHECK-NEXT: vmov.16 q0[1], r2
|
||||
; CHECK-NEXT: vstrb.8 q4, [r1, #64]!
|
||||
; CHECK-NEXT: vmov.16 q0[2], r0
|
||||
; CHECK-NEXT: vmov r0, s22
|
||||
; CHECK-NEXT: vmov.16 q0[3], r0
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmovx.f16 s4, s10
|
||||
; CHECK-NEXT: vmov.16 q0[4], r0
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmovx.f16 s4, s14
|
||||
; CHECK-NEXT: vmov.16 q0[5], r0
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmovx.f16 s4, s22
|
||||
; CHECK-NEXT: vmov.16 q0[6], r0
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmov q4, q6
|
||||
; CHECK-NEXT: vmov.16 q0[7], r0
|
||||
; CHECK-NEXT: vmov r0, s19
|
||||
; CHECK-NEXT: vstrh.16 q0, [r1, #32]
|
||||
; CHECK-NEXT: vmov.16 q0[0], r0
|
||||
; CHECK-NEXT: vmov r2, s11
|
||||
; CHECK-NEXT: vmovx.f16 s4, s19
|
||||
; CHECK-NEXT: vmov.16 q0[1], r2
|
||||
; CHECK-NEXT: vmov r0, s15
|
||||
; CHECK-NEXT: vmov.16 q0[2], r0
|
||||
; CHECK-NEXT: vmov r0, s23
|
||||
; CHECK-NEXT: vmov.16 q0[3], r0
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmovx.f16 s4, s11
|
||||
; CHECK-NEXT: vmov.16 q0[4], r0
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmovx.f16 s4, s15
|
||||
; CHECK-NEXT: vmov.16 q0[5], r0
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmovx.f16 s4, s23
|
||||
; CHECK-NEXT: vmov.16 q0[6], r0
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmovx.f16 s4, s17
|
||||
; CHECK-NEXT: vmov.16 q0[7], r0
|
||||
; CHECK-NEXT: vmov r2, s17
|
||||
; CHECK-NEXT: vstrh.16 q0, [r1, #48]
|
||||
; CHECK-NEXT: vmov r0, s9
|
||||
; CHECK-NEXT: vmov.16 q0[0], r2
|
||||
; CHECK-NEXT: vmov.16 q0[1], r0
|
||||
; CHECK-NEXT: vmov r0, s13
|
||||
; CHECK-NEXT: vmov.16 q0[2], r0
|
||||
; CHECK-NEXT: vmov r0, s21
|
||||
; CHECK-NEXT: vmov.16 q0[3], r0
|
||||
; CHECK-NEXT: vmov r2, s25
|
||||
; CHECK-NEXT: vmov.16 q3[2], r0
|
||||
; CHECK-NEXT: vmovx.f16 s0, s21
|
||||
; CHECK-NEXT: vmov.16 q3[3], r2
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmovx.f16 s0, s25
|
||||
; CHECK-NEXT: vmov.16 q3[6], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmov.16 q3[7], r0
|
||||
; CHECK-NEXT: vmov r0, s5
|
||||
; CHECK-NEXT: vmov r2, s9
|
||||
; CHECK-NEXT: vmov.16 q7[0], r0
|
||||
; CHECK-NEXT: vmovx.f16 s0, s5
|
||||
; CHECK-NEXT: vmov.16 q7[1], r2
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmovx.f16 s0, s9
|
||||
; CHECK-NEXT: vmov.16 q7[4], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmov.16 q7[5], r0
|
||||
; CHECK-NEXT: vmov r0, s20
|
||||
; CHECK-NEXT: vstrw.32 q3, [sp] @ 16-byte Spill
|
||||
; CHECK-NEXT: vmovx.f16 s0, s20
|
||||
; CHECK-NEXT: vmov.16 q3[2], r0
|
||||
; CHECK-NEXT: vmov r2, s24
|
||||
; CHECK-NEXT: vmov.16 q3[3], r2
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmovx.f16 s0, s24
|
||||
; CHECK-NEXT: vmov.16 q3[6], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmovx.f16 s20, s22
|
||||
; CHECK-NEXT: vmov.16 q3[7], r0
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmovx.f16 s4, s9
|
||||
; CHECK-NEXT: vmov r2, s8
|
||||
; CHECK-NEXT: vmov.16 q0[0], r0
|
||||
; CHECK-NEXT: vmovx.f16 s4, s4
|
||||
; CHECK-NEXT: vmov.16 q0[1], r2
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmovx.f16 s4, s8
|
||||
; CHECK-NEXT: vmov.16 q0[4], r0
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmovx.f16 s4, s13
|
||||
; CHECK-NEXT: vmov.16 q0[5], r0
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmovx.f16 s4, s21
|
||||
; CHECK-NEXT: vmov.16 q0[6], r0
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmov.16 q0[7], r0
|
||||
; CHECK-NEXT: vstrh.16 q0, [r1, #16]
|
||||
; CHECK-NEXT: vmov r0, s22
|
||||
; CHECK-NEXT: vmov.16 q1[2], r0
|
||||
; CHECK-NEXT: vmov r2, s26
|
||||
; CHECK-NEXT: vmov r0, s20
|
||||
; CHECK-NEXT: vmov.16 q1[3], r2
|
||||
; CHECK-NEXT: vmovx.f16 s20, s26
|
||||
; CHECK-NEXT: vmov.16 q1[6], r0
|
||||
; CHECK-NEXT: vmov r0, s20
|
||||
; CHECK-NEXT: vmovx.f16 s20, s10
|
||||
; CHECK-NEXT: vmov.16 q1[7], r0
|
||||
; CHECK-NEXT: vmov r0, s20
|
||||
; CHECK-NEXT: vldrw.u32 q5, [sp, #64] @ 16-byte Reload
|
||||
; CHECK-NEXT: vldrw.u32 q2, [sp] @ 16-byte Reload
|
||||
; CHECK-NEXT: vldrw.u32 q6, [sp, #48] @ 16-byte Reload
|
||||
; CHECK-NEXT: vmov.f32 s1, s13
|
||||
; CHECK-NEXT: vmov.f32 s29, s9
|
||||
; CHECK-NEXT: vmov.16 q5[5], r0
|
||||
; CHECK-NEXT: vmov.f32 s31, s11
|
||||
; CHECK-NEXT: vmov q2, q5
|
||||
; CHECK-NEXT: vmov.f32 s17, s25
|
||||
; CHECK-NEXT: vmov.f32 s9, s5
|
||||
; CHECK-NEXT: vmov.f32 s3, s15
|
||||
; CHECK-NEXT: vstrb.8 q0, [r1, #64]!
|
||||
; CHECK-NEXT: vmov.f32 s19, s27
|
||||
; CHECK-NEXT: vmov.f32 s11, s7
|
||||
; CHECK-NEXT: vstrh.16 q4, [r1, #48]
|
||||
; CHECK-NEXT: vstrh.16 q2, [r1, #32]
|
||||
; CHECK-NEXT: vstrh.16 q7, [r1, #16]
|
||||
; CHECK-NEXT: le lr, .LBB0_2
|
||||
; CHECK-NEXT: .LBB0_3: @ %while.end
|
||||
; CHECK-NEXT: add sp, #40
|
||||
; CHECK-NEXT: add sp, #104
|
||||
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
|
||||
; CHECK-NEXT: pop {r7, pc}
|
||||
entry:
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -858,38 +858,31 @@ entry:
|
|||
define void @vst4_v2f16(<2 x half> *%src, <8 x half> *%dst) {
|
||||
; CHECK-LABEL: vst4_v2f16:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .save {r4, lr}
|
||||
; CHECK-NEXT: push {r4, lr}
|
||||
; CHECK-NEXT: ldrd r3, r12, [r0]
|
||||
; CHECK-NEXT: vldmia r0, {s4, s5}
|
||||
; CHECK-NEXT: vmov r2, s5
|
||||
; CHECK-NEXT: ldr r0, [r0, #8]
|
||||
; CHECK-NEXT: vmov.32 q1[0], r3
|
||||
; CHECK-NEXT: vmov.32 q2[0], r12
|
||||
; CHECK-NEXT: vmov r3, s4
|
||||
; CHECK-NEXT: vmovx.f16 s4, s4
|
||||
; CHECK-NEXT: vmov.32 q0[0], r0
|
||||
; CHECK-NEXT: vmov r2, s4
|
||||
; CHECK-NEXT: vmov.16 q1[0], r3
|
||||
; CHECK-NEXT: vmov lr, s0
|
||||
; CHECK-NEXT: vmov.16 q1[1], r2
|
||||
; CHECK-NEXT: vmovx.f16 s0, s0
|
||||
; CHECK-NEXT: vmov r3, s4
|
||||
; CHECK-NEXT: vmov r4, s0
|
||||
; CHECK-NEXT: vmov.16 q0[0], lr
|
||||
; CHECK-NEXT: vmov.16 q0[1], r4
|
||||
; CHECK-NEXT: vmovx.f16 s12, s4
|
||||
; CHECK-NEXT: vmov.16 q0[0], r3
|
||||
; CHECK-NEXT: vdup.32 q2, r0
|
||||
; CHECK-NEXT: vmov.16 q0[1], r2
|
||||
; CHECK-NEXT: vmov r0, s8
|
||||
; CHECK-NEXT: vmov.16 q1[0], r3
|
||||
; CHECK-NEXT: vmov.16 q1[1], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmov.16 q1[2], r0
|
||||
; CHECK-NEXT: vmovx.f16 s0, s8
|
||||
; CHECK-NEXT: vmov.16 q1[3], lr
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmov.16 q1[4], r2
|
||||
; CHECK-NEXT: vmov.16 q1[5], r0
|
||||
; CHECK-NEXT: vmov.16 q1[6], r4
|
||||
; CHECK-NEXT: vmov.16 q1[7], r4
|
||||
; CHECK-NEXT: vstrw.32 q1, [r1]
|
||||
; CHECK-NEXT: pop {r4, pc}
|
||||
; CHECK-NEXT: vmov.16 q0[2], r0
|
||||
; CHECK-NEXT: vmov r0, s9
|
||||
; CHECK-NEXT: vmov.16 q0[3], r0
|
||||
; CHECK-NEXT: vmov r0, s12
|
||||
; CHECK-NEXT: vmovx.f16 s4, s5
|
||||
; CHECK-NEXT: vmov.16 q0[4], r0
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmovx.f16 s4, s8
|
||||
; CHECK-NEXT: vmov.16 q0[5], r0
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmovx.f16 s4, s9
|
||||
; CHECK-NEXT: vmov.16 q0[6], r0
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmov.16 q0[7], r0
|
||||
; CHECK-NEXT: vstrw.32 q0, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%s1 = getelementptr <2 x half>, <2 x half>* %src, i32 0
|
||||
%l1 = load <2 x half>, <2 x half>* %s1, align 4
|
||||
|
|
@ -909,73 +902,61 @@ entry:
|
|||
define void @vst4_v4f16(<4 x half> *%src, <16 x half> *%dst) {
|
||||
; CHECK-LABEL: vst4_v4f16:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .save {r4, r5, r6, lr}
|
||||
; CHECK-NEXT: push {r4, r5, r6, lr}
|
||||
; CHECK-NEXT: .vsave {d8}
|
||||
; CHECK-NEXT: vpush {d8}
|
||||
; CHECK-NEXT: ldrd r2, r3, [r0, #16]
|
||||
; CHECK-NEXT: ldm.w r0, {r4, r5, r6}
|
||||
; CHECK-NEXT: .save {r7, lr}
|
||||
; CHECK-NEXT: push {r7, lr}
|
||||
; CHECK-NEXT: ldm.w r0, {r2, r3, r12, lr}
|
||||
; CHECK-NEXT: vmov.32 q0[0], r2
|
||||
; CHECK-NEXT: vmov.32 q0[1], r3
|
||||
; CHECK-NEXT: vmov.32 q0[2], r12
|
||||
; CHECK-NEXT: vmov.32 q0[3], lr
|
||||
; CHECK-NEXT: vmov r3, s1
|
||||
; CHECK-NEXT: vmovx.f16 s12, s1
|
||||
; CHECK-NEXT: vmov r2, s3
|
||||
; CHECK-NEXT: vmov.16 q2[0], r3
|
||||
; CHECK-NEXT: vmov.16 q2[1], r2
|
||||
; CHECK-NEXT: ldrd r2, r0, [r0, #16]
|
||||
; CHECK-NEXT: vmov.32 q1[0], r2
|
||||
; CHECK-NEXT: vmov.32 q1[1], r3
|
||||
; CHECK-NEXT: ldr r0, [r0, #12]
|
||||
; CHECK-NEXT: vmov.32 q2[0], r4
|
||||
; CHECK-NEXT: vmov.32 q1[1], r0
|
||||
; CHECK-NEXT: vmov.32 q1[2], r2
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: vmov.32 q1[3], r0
|
||||
; CHECK-NEXT: vmov r0, s5
|
||||
; CHECK-NEXT: vmov.16 q2[2], r0
|
||||
; CHECK-NEXT: vmov r0, s7
|
||||
; CHECK-NEXT: vmov.16 q2[3], r0
|
||||
; CHECK-NEXT: vmov r0, s12
|
||||
; CHECK-NEXT: vmovx.f16 s12, s3
|
||||
; CHECK-NEXT: vmov.16 q2[4], r0
|
||||
; CHECK-NEXT: vmov r0, s12
|
||||
; CHECK-NEXT: vmovx.f16 s12, s5
|
||||
; CHECK-NEXT: vmov.16 q2[5], r0
|
||||
; CHECK-NEXT: vmov r0, s12
|
||||
; CHECK-NEXT: vmovx.f16 s12, s7
|
||||
; CHECK-NEXT: vmov.16 q2[6], r0
|
||||
; CHECK-NEXT: vmov r0, s12
|
||||
; CHECK-NEXT: vmovx.f16 s12, s0
|
||||
; CHECK-NEXT: vmov.16 q2[7], r0
|
||||
; CHECK-NEXT: vmov r0, s2
|
||||
; CHECK-NEXT: vstrw.32 q2, [r1, #16]
|
||||
; CHECK-NEXT: vmov.16 q2[0], r2
|
||||
; CHECK-NEXT: vmov.16 q2[1], r0
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmov.16 q2[2], r0
|
||||
; CHECK-NEXT: vmov r0, s6
|
||||
; CHECK-NEXT: vmov.16 q2[3], r0
|
||||
; CHECK-NEXT: vmov r0, s12
|
||||
; CHECK-NEXT: vmovx.f16 s0, s2
|
||||
; CHECK-NEXT: vmov.16 q2[4], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmovx.f16 s0, s4
|
||||
; CHECK-NEXT: vmov lr, s4
|
||||
; CHECK-NEXT: vmovx.f16 s4, s5
|
||||
; CHECK-NEXT: vmov.32 q2[1], r5
|
||||
; CHECK-NEXT: vmov r2, s4
|
||||
; CHECK-NEXT: vmovx.f16 s4, s8
|
||||
; CHECK-NEXT: vmov r4, s8
|
||||
; CHECK-NEXT: vmov r3, s5
|
||||
; CHECK-NEXT: vmovx.f16 s8, s9
|
||||
; CHECK-NEXT: vmov r5, s4
|
||||
; CHECK-NEXT: vmov.16 q1[0], r4
|
||||
; CHECK-NEXT: vmov.16 q1[1], r5
|
||||
; CHECK-NEXT: vmov r4, s9
|
||||
; CHECK-NEXT: vmov r12, s0
|
||||
; CHECK-NEXT: vmov.16 q0[0], lr
|
||||
; CHECK-NEXT: vmov.16 q1[2], r4
|
||||
; CHECK-NEXT: vmov r4, s8
|
||||
; CHECK-NEXT: vmov.16 q0[1], r12
|
||||
; CHECK-NEXT: vmov.32 q2[0], r6
|
||||
; CHECK-NEXT: vmov.16 q1[3], r4
|
||||
; CHECK-NEXT: vmov.32 q2[1], r0
|
||||
; CHECK-NEXT: vmov.16 q0[2], r3
|
||||
; CHECK-NEXT: vmov r5, s5
|
||||
; CHECK-NEXT: vmov.16 q0[3], r2
|
||||
; CHECK-NEXT: vmov r0, s9
|
||||
; CHECK-NEXT: vmov.16 q3[0], r5
|
||||
; CHECK-NEXT: vmovx.f16 s16, s9
|
||||
; CHECK-NEXT: vmov.16 q3[1], r0
|
||||
; CHECK-NEXT: vmov r0, s1
|
||||
; CHECK-NEXT: vmov.16 q3[2], r0
|
||||
; CHECK-NEXT: vmov r0, s16
|
||||
; CHECK-NEXT: vmov.16 q3[3], r3
|
||||
; CHECK-NEXT: vmov.16 q3[4], r4
|
||||
; CHECK-NEXT: vmov.16 q3[5], r0
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmov.16 q3[6], r2
|
||||
; CHECK-NEXT: vmovx.f16 s4, s4
|
||||
; CHECK-NEXT: vmov.16 q3[7], r2
|
||||
; CHECK-NEXT: vmov r2, s8
|
||||
; CHECK-NEXT: vstrw.32 q3, [r1, #16]
|
||||
; CHECK-NEXT: vmov.16 q3[0], r0
|
||||
; CHECK-NEXT: vmov.16 q2[5], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmov.16 q3[1], r2
|
||||
; CHECK-NEXT: vmov.16 q3[2], r0
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmov.16 q3[3], lr
|
||||
; CHECK-NEXT: vmovx.f16 s4, s8
|
||||
; CHECK-NEXT: vmov.16 q3[4], r0
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmovx.f16 s0, s0
|
||||
; CHECK-NEXT: vmov.16 q3[5], r0
|
||||
; CHECK-NEXT: vmovx.f16 s0, s6
|
||||
; CHECK-NEXT: vmov.16 q2[6], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmov.16 q3[6], r0
|
||||
; CHECK-NEXT: vmov.16 q3[7], r12
|
||||
; CHECK-NEXT: vstrw.32 q3, [r1]
|
||||
; CHECK-NEXT: vpop {d8}
|
||||
; CHECK-NEXT: pop {r4, r5, r6, pc}
|
||||
; CHECK-NEXT: vmov.16 q2[7], r0
|
||||
; CHECK-NEXT: vstrw.32 q2, [r1]
|
||||
; CHECK-NEXT: pop {r7, pc}
|
||||
entry:
|
||||
%s1 = getelementptr <4 x half>, <4 x half>* %src, i32 0
|
||||
%l1 = load <4 x half>, <4 x half>* %s1, align 4
|
||||
|
|
|
|||
Loading…
Reference in New Issue