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[SystemZ] Implement isLegalAddressingMode() 

The loop optimizers were assuming that scales > 1 were OK.  I think this
is actually a bug in TargetLoweringBase::isLegalAddressingMode(),
since it seems to be trying to reject anything that isn't r+i or r+r,
but it has no default case for scales other than 0, 1 or 2.  Implementing
the hook for z means that z can no longer test any change there though.

llvm-svn: 187497
This commit is contained in:
Richard Sandiford 2013-07-31 12:58:26 +00:00
parent ee8343822e
commit 791bea4182
3 changed files with 46 additions and 3 deletions
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15
llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
View File

@ -290,6 +290,21 @@ bool SystemZTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
return true;
}
bool SystemZTargetLowering::isLegalAddressingMode(const AddrMode &AM,
Type *Ty) const {
// Punt on globals for now, although they can be used in limited
// RELATIVE LONG cases.
if (AM.BaseGV)
return false;
// Require a 20-bit signed offset.
if (!isInt<20>(AM.BaseOffs))
return false;
// Indexing is OK but no scale factor can be applied.
return AM.Scale == 0 || AM.Scale == 1;
}
//===----------------------------------------------------------------------===//
// Inline asm support
//===----------------------------------------------------------------------===//

9
llvm/lib/Target/SystemZ/SystemZISelLowering.h
View File

@ -126,12 +126,15 @@ public:
virtual MVT getScalarShiftAmountTy(EVT LHSTy) const LLVM_OVERRIDE {
return MVT::i32;
}
virtual EVT getSetCCResultType(LLVMContext &, EVT) const {
virtual EVT getSetCCResultType(LLVMContext &, EVT) const LLVM_OVERRIDE {
return MVT::i32;
}
virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const LLVM_OVERRIDE;
virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const;
virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const LLVM_OVERRIDE;
virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const
LLVM_OVERRIDE;
virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const
LLVM_OVERRIDE;
virtual const char *getTargetNodeName(unsigned Opcode) const LLVM_OVERRIDE;
virtual std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const std::string &Constraint,

25
llvm/test/CodeGen/SystemZ/loop-01.ll Normal file
View File

@ -0,0 +1,25 @@
; Test loop tuning.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
; Test that strength reduction is applied to addresses with a scale factor,
; but that indexed addressing can still be used.
define void @f1(i32 *%dest, i32 %a) {
; CHECK-LABEL: f1
; CHECK-NOT: sllg
; CHECK: st %r3, 0({{%r[1-5],%r[1-5]}})
; CHECK: br %r14
entry:
br label %loop
loop:
%index = phi i64 [ 0, %entry ], [ %next, %loop ]
%ptr = getelementptr i32 *%dest, i64 %index
store i32 %a, i32 *%ptr
%next = add i64 %index, 1
%cmp = icmp ne i64 %next, 100
br i1 %cmp, label %loop, label %exit
exit:
ret void
}