maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[AArch64][SVE] Asm: Support for EXT instruction. 

This patch adds an instruction that allows extracting
a vector from a pair of vectors, given an immediate index
that describes the element position to extract from.

The instruction has the following assembly:
  ext z0.b, z0.b, z1.b, #imm

where #imm is an immediate between 0 and 255.

llvm-svn: 337251
This commit is contained in:
Sander de Smalen 2018-07-17 08:39:48 +00:00
parent e25b1c35bb
commit 78fe30a662
4 changed files with 74 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
View File

@ -115,6 +115,7 @@ let Predicates = [HasSVE] in {
defm COMPACT_ZPZ : sve_int_perm_compact<"compact">;
defm INSR_ZR : sve_int_perm_insrs<"insr">;
defm INSR_ZV : sve_int_perm_insrv<"insr">;
def EXT_ZZI : sve_int_perm_extract_i<"ext">;
defm SUNPKLO_ZZ : sve_int_perm_unpk<0b00, "sunpklo">;
defm SUNPKHI_ZZ : sve_int_perm_unpk<0b01, "sunpkhi">;

20
llvm/lib/Target/AArch64/SVEInstrFormats.td
View File

@ -728,6 +728,26 @@ multiclass sve_int_perm_insrv<string asm> {
def _D : sve_int_perm_insrv<0b11, asm, ZPR64, FPR64>;
}
//===----------------------------------------------------------------------===//
// SVE Permute - Extract Group
//===----------------------------------------------------------------------===//
class sve_int_perm_extract_i<string asm>
: I<(outs ZPR8:$Zdn), (ins ZPR8:$_Zdn, ZPR8:$Zm, imm0_255:$imm8),
asm, "\t$Zdn, $_Zdn, $Zm, $imm8",
"", []>, Sched<[]> {
bits<5> Zdn;
bits<5> Zm;
bits<8> imm8;
let Inst{31-21} = 0b00000101001;
let Inst{20-16} = imm8{7-3};
let Inst{15-13} = 0b000;
let Inst{12-10} = imm8{2-0};
let Inst{9-5} = Zm;
let Inst{4-0} = Zdn;
let Constraints = "$Zdn = $_Zdn";
}
//===----------------------------------------------------------------------===//
// SVE Vector Select Group

33
llvm/test/MC/AArch64/SVE/ext-diagnostics.s Normal file
View File

@ -0,0 +1,33 @@
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Tied operands must match
ext z0.b, z1.b, z2.b, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: ext z0.b, z1.b, z2.b, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element widths.
ext z0.h, z0.h, z1.h, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ext z0.h, z0.h, z1.h, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid immediate range.
ext z0.b, z0.b, z1.b, #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255].
// CHECK-NEXT: ext z0.b, z0.b, z1.b, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ext z0.b, z0.b, z1.b, #256
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255].
// CHECK-NEXT: ext z0.b, z0.b, z1.b, #256
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

20
llvm/test/MC/AArch64/SVE/ext.s Normal file
View File

@ -0,0 +1,20 @@
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
ext z31.b, z31.b, z0.b, #0
// CHECK-INST: ext z31.b, z31.b, z0.b, #0
// CHECK-ENCODING: [0x1f,0x00,0x20,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 1f 00 20 05 <unknown>
ext z31.b, z31.b, z0.b, #255
// CHECK-INST: ext z31.b, z31.b, z0.b, #255
// CHECK-ENCODING: [0x1f,0x1c,0x3f,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 1f 1c 3f 05 <unknown>