forked from OSchip/llvm-project
[NFC][InstCombine] Add shift amount reassociation in bittest tests (PR42399)
https://bugs.llvm.org/show_bug.cgi?id=42399 https://rise4fun.com/Alive/kBb https://rise4fun.com/Alive/1SB llvm-svn: 364430
This commit is contained in:
Roman Lebedev
parent
24f96a0eee
commit
78edfc4bf0
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@ -0,0 +1,420 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt %s -instcombine -S | FileCheck %s
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; Given pattern:
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; icmp eq/ne (and ((x shift Q), (y oppositeshift K))), 0
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; we should move shifts to the same hand of 'and', i.e. e.g. rewrite as
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; icmp eq/ne (and (((x shift Q) shift K), y)), 0
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; We are only interested in opposite logical shifts here.
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; Basic scalar test with constants
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define i1 @t0_const_lshr_shl_ne(i32 %x, i32 %y) {
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; CHECK-LABEL: @t0_const_lshr_shl_ne(
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; CHECK-NEXT: [[T0:%.*]] = lshr i32 [[X:%.*]], 1
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; CHECK-NEXT: [[T1:%.*]] = shl i32 [[Y:%.*]], 1
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; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[T0]]
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; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 0
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; CHECK-NEXT: ret i1 [[T3]]
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;
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%t0 = lshr i32 %x, 1
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%t1 = shl i32 %y, 1
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%t2 = and i32 %t1, %t0
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%t3 = icmp ne i32 %t2, 0
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ret i1 %t3
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}
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define i1 @t1_const_shl_lshr_ne(i32 %x, i32 %y) {
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; CHECK-LABEL: @t1_const_shl_lshr_ne(
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; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], 1
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; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[Y:%.*]], 1
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; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[T0]]
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; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 0
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; CHECK-NEXT: ret i1 [[T3]]
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;
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%t0 = shl i32 %x, 1
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%t1 = lshr i32 %y, 1
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%t2 = and i32 %t1, %t0
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%t3 = icmp ne i32 %t2, 0
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ret i1 %t3
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}
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; We are ok with 'eq' predicate too.
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define i1 @t2_const_lshr_shl_eq(i32 %x, i32 %y) {
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; CHECK-LABEL: @t2_const_lshr_shl_eq(
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; CHECK-NEXT: [[T0:%.*]] = lshr i32 [[X:%.*]], 1
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; CHECK-NEXT: [[T1:%.*]] = shl i32 [[Y:%.*]], 1
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; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[T0]]
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; CHECK-NEXT: [[T3:%.*]] = icmp eq i32 [[T2]], 0
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; CHECK-NEXT: ret i1 [[T3]]
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;
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%t0 = lshr i32 %x, 1
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%t1 = shl i32 %y, 1
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%t2 = and i32 %t1, %t0
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%t3 = icmp eq i32 %t2, 0
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ret i1 %t3
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}
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; Basic scalar test with constants after folding
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define i1 @t3_const_after_fold_lshr_shl_ne(i32 %x, i32 %y, i32 %len) {
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; CHECK-LABEL: @t3_const_after_fold_lshr_shl_ne(
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; CHECK-NEXT: [[T0:%.*]] = sub i32 32, [[LEN:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[X:%.*]], [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = add i32 [[LEN]], -1
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; CHECK-NEXT: [[T3:%.*]] = shl i32 [[Y:%.*]], [[T2]]
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; CHECK-NEXT: [[T4:%.*]] = and i32 [[T1]], [[T3]]
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; CHECK-NEXT: [[T5:%.*]] = icmp ne i32 [[T4]], 0
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; CHECK-NEXT: ret i1 [[T5]]
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;
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%t0 = sub i32 32, %len
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%t1 = lshr i32 %x, %t0
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%t2 = add i32 %len, -1
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%t3 = shl i32 %y, %t2
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%t4 = and i32 %t1, %t3
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%t5 = icmp ne i32 %t4, 0
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ret i1 %t5
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}
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define i1 @t4_const_after_fold_lshr_shl_ne(i32 %x, i32 %y, i32 %len) {
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; CHECK-LABEL: @t4_const_after_fold_lshr_shl_ne(
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; CHECK-NEXT: [[T0:%.*]] = sub i32 32, [[LEN:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = shl i32 [[X:%.*]], [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = add i32 [[LEN]], -1
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; CHECK-NEXT: [[T3:%.*]] = lshr i32 [[Y:%.*]], [[T2]]
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; CHECK-NEXT: [[T4:%.*]] = and i32 [[T1]], [[T3]]
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; CHECK-NEXT: [[T5:%.*]] = icmp ne i32 [[T4]], 0
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; CHECK-NEXT: ret i1 [[T5]]
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;
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%t0 = sub i32 32, %len
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%t1 = shl i32 %x, %t0
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%t2 = add i32 %len, -1
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%t3 = lshr i32 %y, %t2
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%t4 = and i32 %t1, %t3
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%t5 = icmp ne i32 %t4, 0
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ret i1 %t5
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}
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; Completely variable shift amounts
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define i1 @t5_const_lshr_shl_ne(i32 %x, i32 %y, i32 %shamt0, i32 %shamt1) {
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; CHECK-LABEL: @t5_const_lshr_shl_ne(
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; CHECK-NEXT: [[T0:%.*]] = lshr i32 [[X:%.*]], [[SHAMT0:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = shl i32 [[Y:%.*]], [[SHAMT1:%.*]]
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; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[T0]]
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; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 0
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; CHECK-NEXT: ret i1 [[T3]]
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;
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%t0 = lshr i32 %x, %shamt0
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%t1 = shl i32 %y, %shamt1
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%t2 = and i32 %t1, %t0
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%t3 = icmp ne i32 %t2, 0
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ret i1 %t3
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}
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define i1 @t6_const_shl_lshr_ne(i32 %x, i32 %y, i32 %shamt0, i32 %shamt1) {
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; CHECK-LABEL: @t6_const_shl_lshr_ne(
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; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[SHAMT0:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[Y:%.*]], [[SHAMT1:%.*]]
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; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[T0]]
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; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 0
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; CHECK-NEXT: ret i1 [[T3]]
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;
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%t0 = shl i32 %x, %shamt0
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%t1 = lshr i32 %y, %shamt1
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%t2 = and i32 %t1, %t0
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%t3 = icmp ne i32 %t2, 0
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ret i1 %t3
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}
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; Very basic vector tests
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define <2 x i1> @t7_const_lshr_shl_ne_vec_splat(<2 x i32> %x, <2 x i32> %y) {
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; CHECK-LABEL: @t7_const_lshr_shl_ne_vec_splat(
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; CHECK-NEXT: [[T0:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 1, i32 1>
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; CHECK-NEXT: [[T1:%.*]] = shl <2 x i32> [[Y:%.*]], <i32 1, i32 1>
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; CHECK-NEXT: [[T2:%.*]] = and <2 x i32> [[T1]], [[T0]]
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; CHECK-NEXT: [[T3:%.*]] = icmp ne <2 x i32> [[T2]], zeroinitializer
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; CHECK-NEXT: ret <2 x i1> [[T3]]
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;
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%t0 = lshr <2 x i32> %x, <i32 1, i32 1>
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%t1 = shl <2 x i32> %y, <i32 1, i32 1>
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%t2 = and <2 x i32> %t1, %t0
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%t3 = icmp ne <2 x i32> %t2, <i32 0, i32 0>
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ret <2 x i1> %t3
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}
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define <2 x i1> @t8_const_lshr_shl_ne_vec_nonsplat(<2 x i32> %x, <2 x i32> %y) {
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; CHECK-LABEL: @t8_const_lshr_shl_ne_vec_nonsplat(
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; CHECK-NEXT: [[T0:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 1, i32 2>
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; CHECK-NEXT: [[T1:%.*]] = shl <2 x i32> [[Y:%.*]], <i32 3, i32 4>
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; CHECK-NEXT: [[T2:%.*]] = and <2 x i32> [[T1]], [[T0]]
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; CHECK-NEXT: [[T3:%.*]] = icmp ne <2 x i32> [[T2]], zeroinitializer
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; CHECK-NEXT: ret <2 x i1> [[T3]]
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;
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%t0 = lshr <2 x i32> %x, <i32 1, i32 2>
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%t1 = shl <2 x i32> %y, <i32 3, i32 4>
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%t2 = and <2 x i32> %t1, %t0
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%t3 = icmp ne <2 x i32> %t2, <i32 0, i32 0>
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ret <2 x i1> %t3
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}
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define <3 x i1> @t9_const_lshr_shl_ne_vec_undef0(<3 x i32> %x, <3 x i32> %y) {
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; CHECK-LABEL: @t9_const_lshr_shl_ne_vec_undef0(
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; CHECK-NEXT: [[T0:%.*]] = lshr <3 x i32> [[X:%.*]], <i32 1, i32 undef, i32 1>
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; CHECK-NEXT: [[T1:%.*]] = shl <3 x i32> [[Y:%.*]], <i32 1, i32 1, i32 1>
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; CHECK-NEXT: [[T2:%.*]] = and <3 x i32> [[T1]], [[T0]]
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; CHECK-NEXT: [[T3:%.*]] = icmp ne <3 x i32> [[T2]], zeroinitializer
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; CHECK-NEXT: ret <3 x i1> [[T3]]
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;
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%t0 = lshr <3 x i32> %x, <i32 1, i32 undef, i32 1>
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%t1 = shl <3 x i32> %y, <i32 1, i32 1, i32 1>
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%t2 = and <3 x i32> %t1, %t0
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%t3 = icmp ne <3 x i32> %t2, <i32 0, i32 0, i32 0>
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ret <3 x i1> %t3
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}
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define <3 x i1> @t10_const_lshr_shl_ne_vec_undef1(<3 x i32> %x, <3 x i32> %y) {
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; CHECK-LABEL: @t10_const_lshr_shl_ne_vec_undef1(
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; CHECK-NEXT: [[T0:%.*]] = lshr <3 x i32> [[X:%.*]], <i32 1, i32 1, i32 1>
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; CHECK-NEXT: [[T1:%.*]] = shl <3 x i32> [[Y:%.*]], <i32 1, i32 undef, i32 1>
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; CHECK-NEXT: [[T2:%.*]] = and <3 x i32> [[T1]], [[T0]]
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; CHECK-NEXT: [[T3:%.*]] = icmp ne <3 x i32> [[T2]], zeroinitializer
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; CHECK-NEXT: ret <3 x i1> [[T3]]
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;
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%t0 = lshr <3 x i32> %x, <i32 1, i32 1, i32 1>
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%t1 = shl <3 x i32> %y, <i32 1, i32 undef, i32 1>
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%t2 = and <3 x i32> %t1, %t0
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%t3 = icmp ne <3 x i32> %t2, <i32 0, i32 0, i32 0>
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ret <3 x i1> %t3
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}
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define <3 x i1> @t11_const_lshr_shl_ne_vec_undef2(<3 x i32> %x, <3 x i32> %y) {
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; CHECK-LABEL: @t11_const_lshr_shl_ne_vec_undef2(
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; CHECK-NEXT: [[T0:%.*]] = lshr <3 x i32> [[X:%.*]], <i32 1, i32 1, i32 1>
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; CHECK-NEXT: [[T1:%.*]] = shl <3 x i32> [[Y:%.*]], <i32 1, i32 1, i32 1>
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; CHECK-NEXT: [[T2:%.*]] = and <3 x i32> [[T1]], [[T0]]
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; CHECK-NEXT: [[T3:%.*]] = icmp ne <3 x i32> [[T2]], <i32 0, i32 undef, i32 0>
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; CHECK-NEXT: ret <3 x i1> [[T3]]
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;
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%t0 = lshr <3 x i32> %x, <i32 1, i32 1, i32 1>
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%t1 = shl <3 x i32> %y, <i32 1, i32 1, i32 1>
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%t2 = and <3 x i32> %t1, %t0
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%t3 = icmp ne <3 x i32> %t2, <i32 0, i32 undef, i32 0>
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ret <3 x i1> %t3
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}
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define <3 x i1> @t12_const_lshr_shl_ne_vec_undef3(<3 x i32> %x, <3 x i32> %y) {
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; CHECK-LABEL: @t12_const_lshr_shl_ne_vec_undef3(
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; CHECK-NEXT: [[T0:%.*]] = lshr <3 x i32> [[X:%.*]], <i32 1, i32 undef, i32 1>
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; CHECK-NEXT: [[T1:%.*]] = shl <3 x i32> [[Y:%.*]], <i32 1, i32 undef, i32 1>
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; CHECK-NEXT: [[T2:%.*]] = and <3 x i32> [[T1]], [[T0]]
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; CHECK-NEXT: [[T3:%.*]] = icmp ne <3 x i32> [[T2]], zeroinitializer
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; CHECK-NEXT: ret <3 x i1> [[T3]]
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;
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%t0 = lshr <3 x i32> %x, <i32 1, i32 undef, i32 1>
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%t1 = shl <3 x i32> %y, <i32 1, i32 undef, i32 1>
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%t2 = and <3 x i32> %t1, %t0
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%t3 = icmp ne <3 x i32> %t2, <i32 0, i32 0, i32 0>
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ret <3 x i1> %t3
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}
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define <3 x i1> @t13_const_lshr_shl_ne_vec_undef4(<3 x i32> %x, <3 x i32> %y) {
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; CHECK-LABEL: @t13_const_lshr_shl_ne_vec_undef4(
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; CHECK-NEXT: [[T0:%.*]] = lshr <3 x i32> [[X:%.*]], <i32 1, i32 1, i32 1>
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; CHECK-NEXT: [[T1:%.*]] = shl <3 x i32> [[Y:%.*]], <i32 1, i32 undef, i32 1>
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; CHECK-NEXT: [[T2:%.*]] = and <3 x i32> [[T1]], [[T0]]
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; CHECK-NEXT: [[T3:%.*]] = icmp ne <3 x i32> [[T2]], <i32 0, i32 undef, i32 0>
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; CHECK-NEXT: ret <3 x i1> [[T3]]
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;
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%t0 = lshr <3 x i32> %x, <i32 1, i32 1, i32 1>
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%t1 = shl <3 x i32> %y, <i32 1, i32 undef, i32 1>
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%t2 = and <3 x i32> %t1, %t0
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%t3 = icmp ne <3 x i32> %t2, <i32 0, i32 undef, i32 0>
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ret <3 x i1> %t3
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}
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define <3 x i1> @t14_const_lshr_shl_ne_vec_undef5(<3 x i32> %x, <3 x i32> %y) {
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; CHECK-LABEL: @t14_const_lshr_shl_ne_vec_undef5(
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; CHECK-NEXT: [[T0:%.*]] = lshr <3 x i32> [[X:%.*]], <i32 1, i32 undef, i32 1>
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; CHECK-NEXT: [[T1:%.*]] = shl <3 x i32> [[Y:%.*]], <i32 1, i32 1, i32 1>
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; CHECK-NEXT: [[T2:%.*]] = and <3 x i32> [[T1]], [[T0]]
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; CHECK-NEXT: [[T3:%.*]] = icmp ne <3 x i32> [[T2]], <i32 0, i32 undef, i32 0>
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; CHECK-NEXT: ret <3 x i1> [[T3]]
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;
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%t0 = lshr <3 x i32> %x, <i32 1, i32 undef, i32 1>
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%t1 = shl <3 x i32> %y, <i32 1, i32 1, i32 1>
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%t2 = and <3 x i32> %t1, %t0
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%t3 = icmp ne <3 x i32> %t2, <i32 0, i32 undef, i32 0>
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ret <3 x i1> %t3
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}
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define <3 x i1> @t15_const_lshr_shl_ne_vec_undef6(<3 x i32> %x, <3 x i32> %y) {
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; CHECK-LABEL: @t15_const_lshr_shl_ne_vec_undef6(
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; CHECK-NEXT: [[T0:%.*]] = lshr <3 x i32> [[X:%.*]], <i32 1, i32 undef, i32 1>
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; CHECK-NEXT: [[T1:%.*]] = shl <3 x i32> [[Y:%.*]], <i32 1, i32 undef, i32 1>
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; CHECK-NEXT: [[T2:%.*]] = and <3 x i32> [[T1]], [[T0]]
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; CHECK-NEXT: [[T3:%.*]] = icmp ne <3 x i32> [[T2]], <i32 0, i32 undef, i32 0>
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; CHECK-NEXT: ret <3 x i1> [[T3]]
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;
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%t0 = lshr <3 x i32> %x, <i32 1, i32 undef, i32 1>
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%t1 = shl <3 x i32> %y, <i32 1, i32 undef, i32 1>
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%t2 = and <3 x i32> %t1, %t0
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%t3 = icmp ne <3 x i32> %t2, <i32 0, i32 undef, i32 0>
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ret <3 x i1> %t3
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}
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; One-use tests
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declare void @use32(i32)
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define i1 @t16_const_oneuse0(i32 %x, i32 %y) {
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; CHECK-LABEL: @t16_const_oneuse0(
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; CHECK-NEXT: [[T0:%.*]] = lshr i32 [[X:%.*]], 1
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; CHECK-NEXT: [[T1:%.*]] = shl i32 [[Y:%.*]], 1
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; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[T0]]
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; CHECK-NEXT: call void @use32(i32 [[T2]])
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; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 0
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; CHECK-NEXT: ret i1 [[T3]]
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;
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%t0 = lshr i32 %x, 1
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%t1 = shl i32 %y, 1
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%t2 = and i32 %t1, %t0
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call void @use32(i32 %t2)
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%t3 = icmp ne i32 %t2, 0
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ret i1 %t3
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}
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define i1 @t17_const_oneuse1(i32 %x, i32 %y) {
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; CHECK-LABEL: @t17_const_oneuse1(
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; CHECK-NEXT: [[T0:%.*]] = lshr i32 [[X:%.*]], 1
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; CHECK-NEXT: call void @use32(i32 [[T0]])
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; CHECK-NEXT: [[T1:%.*]] = shl i32 [[Y:%.*]], 1
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; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[T0]]
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; CHECK-NEXT: call void @use32(i32 [[T2]])
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; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 0
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; CHECK-NEXT: ret i1 [[T3]]
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;
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%t0 = lshr i32 %x, 1
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call void @use32(i32 %t0)
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%t1 = shl i32 %y, 1
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%t2 = and i32 %t1, %t0
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call void @use32(i32 %t2)
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%t3 = icmp ne i32 %t2, 0
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ret i1 %t3
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}
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define i1 @t18_const_oneuse2(i32 %x, i32 %y) {
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; CHECK-LABEL: @t18_const_oneuse2(
|
||||
; CHECK-NEXT: [[T0:%.*]] = lshr i32 [[X:%.*]], 1
|
||||
; CHECK-NEXT: [[T1:%.*]] = shl i32 [[Y:%.*]], 1
|
||||
; CHECK-NEXT: call void @use32(i32 [[T1]])
|
||||
; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[T0]]
|
||||
; CHECK-NEXT: call void @use32(i32 [[T2]])
|
||||
; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 0
|
||||
; CHECK-NEXT: ret i1 [[T3]]
|
||||
;
|
||||
%t0 = lshr i32 %x, 1
|
||||
%t1 = shl i32 %y, 1
|
||||
call void @use32(i32 %t1)
|
||||
%t2 = and i32 %t1, %t0
|
||||
call void @use32(i32 %t2)
|
||||
%t3 = icmp ne i32 %t2, 0
|
||||
ret i1 %t3
|
||||
}
|
||||
define i1 @t19_const_oneuse2(i32 %x, i32 %y) {
|
||||
; CHECK-LABEL: @t19_const_oneuse2(
|
||||
; CHECK-NEXT: [[T0:%.*]] = lshr i32 [[X:%.*]], 1
|
||||
; CHECK-NEXT: call void @use32(i32 [[T0]])
|
||||
; CHECK-NEXT: [[T1:%.*]] = shl i32 [[Y:%.*]], 1
|
||||
; CHECK-NEXT: call void @use32(i32 [[T1]])
|
||||
; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[T0]]
|
||||
; CHECK-NEXT: call void @use32(i32 [[T2]])
|
||||
; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 0
|
||||
; CHECK-NEXT: ret i1 [[T3]]
|
||||
;
|
||||
%t0 = lshr i32 %x, 1
|
||||
call void @use32(i32 %t0)
|
||||
%t1 = shl i32 %y, 1
|
||||
call void @use32(i32 %t1)
|
||||
%t2 = and i32 %t1, %t0
|
||||
call void @use32(i32 %t2)
|
||||
%t3 = icmp ne i32 %t2, 0
|
||||
ret i1 %t3
|
||||
}
|
||||
|
||||
define i1 @t17_variable_oneuse0(i32 %x, i32 %y, i32 %shamt0, i32 %shamt1) {
|
||||
; CHECK-LABEL: @t17_variable_oneuse0(
|
||||
; CHECK-NEXT: [[T0:%.*]] = lshr i32 [[X:%.*]], [[SHAMT0:%.*]]
|
||||
; CHECK-NEXT: [[T1:%.*]] = shl i32 [[Y:%.*]], [[SHAMT1:%.*]]
|
||||
; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[T0]]
|
||||
; CHECK-NEXT: call void @use32(i32 [[T2]])
|
||||
; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 0
|
||||
; CHECK-NEXT: ret i1 [[T3]]
|
||||
;
|
||||
%t0 = lshr i32 %x, %shamt0
|
||||
%t1 = shl i32 %y, %shamt1
|
||||
%t2 = and i32 %t1, %t0
|
||||
call void @use32(i32 %t2)
|
||||
%t3 = icmp ne i32 %t2, 0
|
||||
ret i1 %t3
|
||||
}
|
||||
define i1 @t18_variable_oneuse1(i32 %x, i32 %y, i32 %shamt0, i32 %shamt1) {
|
||||
; CHECK-LABEL: @t18_variable_oneuse1(
|
||||
; CHECK-NEXT: [[T0:%.*]] = lshr i32 [[X:%.*]], [[SHAMT0:%.*]]
|
||||
; CHECK-NEXT: call void @use32(i32 [[T0]])
|
||||
; CHECK-NEXT: [[T1:%.*]] = shl i32 [[Y:%.*]], [[SHAMT1:%.*]]
|
||||
; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[T0]]
|
||||
; CHECK-NEXT: call void @use32(i32 [[T2]])
|
||||
; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 0
|
||||
; CHECK-NEXT: ret i1 [[T3]]
|
||||
;
|
||||
%t0 = lshr i32 %x, %shamt0
|
||||
call void @use32(i32 %t0)
|
||||
%t1 = shl i32 %y, %shamt1
|
||||
%t2 = and i32 %t1, %t0
|
||||
call void @use32(i32 %t2)
|
||||
%t3 = icmp ne i32 %t2, 0
|
||||
ret i1 %t3
|
||||
}
|
||||
define i1 @t19_variable_oneuse2(i32 %x, i32 %y, i32 %shamt0, i32 %shamt1) {
|
||||
; CHECK-LABEL: @t19_variable_oneuse2(
|
||||
; CHECK-NEXT: [[T0:%.*]] = lshr i32 [[X:%.*]], [[SHAMT0:%.*]]
|
||||
; CHECK-NEXT: [[T1:%.*]] = shl i32 [[Y:%.*]], [[SHAMT1:%.*]]
|
||||
; CHECK-NEXT: call void @use32(i32 [[T1]])
|
||||
; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[T0]]
|
||||
; CHECK-NEXT: call void @use32(i32 [[T2]])
|
||||
; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 0
|
||||
; CHECK-NEXT: ret i1 [[T3]]
|
||||
;
|
||||
%t0 = lshr i32 %x, %shamt0
|
||||
%t1 = shl i32 %y, %shamt1
|
||||
call void @use32(i32 %t1)
|
||||
%t2 = and i32 %t1, %t0
|
||||
call void @use32(i32 %t2)
|
||||
%t3 = icmp ne i32 %t2, 0
|
||||
ret i1 %t3
|
||||
}
|
||||
define i1 @t20_variable_oneuse2(i32 %x, i32 %y, i32 %shamt0, i32 %shamt1) {
|
||||
; CHECK-LABEL: @t20_variable_oneuse2(
|
||||
; CHECK-NEXT: [[T0:%.*]] = lshr i32 [[X:%.*]], [[SHAMT0:%.*]]
|
||||
; CHECK-NEXT: call void @use32(i32 [[T0]])
|
||||
; CHECK-NEXT: [[T1:%.*]] = shl i32 [[Y:%.*]], [[SHAMT1:%.*]]
|
||||
; CHECK-NEXT: call void @use32(i32 [[T1]])
|
||||
; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[T0]]
|
||||
; CHECK-NEXT: call void @use32(i32 [[T2]])
|
||||
; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 0
|
||||
; CHECK-NEXT: ret i1 [[T3]]
|
||||
;
|
||||
%t0 = lshr i32 %x, %shamt0
|
||||
call void @use32(i32 %t0)
|
||||
%t1 = shl i32 %y, %shamt1
|
||||
call void @use32(i32 %t1)
|
||||
%t2 = and i32 %t1, %t0
|
||||
call void @use32(i32 %t2)
|
||||
%t3 = icmp ne i32 %t2, 0
|
||||
ret i1 %t3
|
||||
}
|
||||
|
||||
; Negative tests
|
||||
define <2 x i1> @n20_overshift(<2 x i32> %x, <2 x i32> %y) {
|
||||
; CHECK-LABEL: @n20_overshift(
|
||||
; CHECK-NEXT: [[T0:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 15, i32 1>
|
||||
; CHECK-NEXT: [[T1:%.*]] = shl <2 x i32> [[Y:%.*]], <i32 17, i32 1>
|
||||
; CHECK-NEXT: [[T2:%.*]] = and <2 x i32> [[T1]], [[T0]]
|
||||
; CHECK-NEXT: [[T3:%.*]] = icmp ne <2 x i32> [[T2]], zeroinitializer
|
||||
; CHECK-NEXT: ret <2 x i1> [[T3]]
|
||||
;
|
||||
%t0 = lshr <2 x i32> %x, <i32 15, i32 1>
|
||||
%t1 = shl <2 x i32> %y, <i32 17, i32 1>
|
||||
%t2 = and <2 x i32> %t1, %t0
|
||||
%t3 = icmp ne <2 x i32> %t2, <i32 0, i32 0>
|
||||
ret <2 x i1> %t3
|
||||
}
|
||||
Loading…
Reference in New Issue