forked from OSchip/llvm-project
parent
c3eb801671
commit
78c5b7a76d
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@ -1164,7 +1164,7 @@ public:
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bool isVarArg, bool isInreg, unsigned NumFixedArgs,
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CallingConv::ID CallConv, bool isTailCall,
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bool isReturnValueUsed, SDValue Callee, ArgListTy &Args,
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SelectionDAG &DAG, DebugLoc dl, unsigned Order);
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SelectionDAG &DAG, DebugLoc dl);
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/// LowerCall - This hook must be implemented to lower calls into the
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/// the specified DAG. The outgoing arguments to the call are described
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@ -1899,8 +1899,7 @@ SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
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TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
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0, TLI.getLibcallCallingConv(LC), false,
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/*isReturnValueUsed=*/true,
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Callee, Args, DAG,
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Node->getDebugLoc(), DAG.GetOrdering(Node));
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Callee, Args, DAG, Node->getDebugLoc());
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// Legalize the call sequence, starting with the chain. This will advance
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// the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
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@ -2308,7 +2307,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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false, false, false, false, 0, CallingConv::C, false,
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/*isReturnValueUsed=*/true,
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DAG.getExternalSymbol("abort", TLI.getPointerTy()),
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Args, DAG, dl, DAG.GetOrdering(Node));
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Args, DAG, dl);
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Results.push_back(CallResult.second);
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break;
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}
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@ -1034,8 +1034,7 @@ SDValue DAGTypeLegalizer::MakeLibCall(RTLIB::Libcall LC, EVT RetVT,
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TLI.LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
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false, 0, TLI.getLibcallCallingConv(LC), false,
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/*isReturnValueUsed=*/true,
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Callee, Args, DAG, dl,
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DAG.GetOrdering(DAG.getEntryNode().getNode()));
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Callee, Args, DAG, dl);
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return CallInfo.first;
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}
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@ -3496,7 +3496,7 @@ SDValue SelectionDAG::getMemcpy(SDValue Chain, DebugLoc dl, SDValue Dst,
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/*isReturnValueUsed=*/false,
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getExternalSymbol(TLI.getLibcallName(RTLIB::MEMCPY),
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TLI.getPointerTy()),
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Args, *this, dl, GetOrdering(Chain.getNode()));
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Args, *this, dl);
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return CallResult.second;
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}
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@ -3545,7 +3545,7 @@ SDValue SelectionDAG::getMemmove(SDValue Chain, DebugLoc dl, SDValue Dst,
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/*isReturnValueUsed=*/false,
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getExternalSymbol(TLI.getLibcallName(RTLIB::MEMMOVE),
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TLI.getPointerTy()),
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Args, *this, dl, GetOrdering(Chain.getNode()));
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Args, *this, dl);
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return CallResult.second;
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}
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@ -3604,7 +3604,7 @@ SDValue SelectionDAG::getMemset(SDValue Chain, DebugLoc dl, SDValue Dst,
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/*isReturnValueUsed=*/false,
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getExternalSymbol(TLI.getLibcallName(RTLIB::MEMSET),
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TLI.getPointerTy()),
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Args, *this, dl, GetOrdering(Chain.getNode()));
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Args, *this, dl);
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return CallResult.second;
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}
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@ -155,7 +155,7 @@ namespace {
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/// this value and returns the result as a ValueVTs value. This uses
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/// Chain/Flag as the input and updates them for the output Chain/Flag.
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/// If the Flag pointer is NULL, no flag is used.
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SDValue getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl, unsigned Order,
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SDValue getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
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SDValue &Chain, SDValue *Flag) const;
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/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
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@ -163,14 +163,14 @@ namespace {
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/// Chain/Flag as the input and updates them for the output Chain/Flag.
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/// If the Flag pointer is NULL, no flag is used.
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void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
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unsigned Order, SDValue &Chain, SDValue *Flag) const;
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SDValue &Chain, SDValue *Flag) const;
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/// AddInlineAsmOperands - Add this value to the specified inlineasm node
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/// operand list. This adds the code marker, matching input operand index
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/// (if applicable), and includes the number of values added into it.
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void AddInlineAsmOperands(unsigned Code,
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bool HasMatching, unsigned MatchingIdx,
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SelectionDAG &DAG, unsigned Order,
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SelectionDAG &DAG,
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std::vector<SDValue> &Ops) const;
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};
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}
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@ -180,7 +180,7 @@ namespace {
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/// larger then ValueVT then AssertOp can be used to specify whether the extra
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/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
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/// (ISD::AssertSext).
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static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl, unsigned Order,
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static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl,
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const SDValue *Parts,
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unsigned NumParts, EVT PartVT, EVT ValueVT,
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ISD::NodeType AssertOp = ISD::DELETED_NODE) {
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@ -205,9 +205,9 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl, unsigned Order,
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EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
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if (RoundParts > 2) {
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Lo = getCopyFromParts(DAG, dl, Order, Parts, RoundParts / 2,
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Lo = getCopyFromParts(DAG, dl, Parts, RoundParts / 2,
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PartVT, HalfVT);
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Hi = getCopyFromParts(DAG, dl, Order, Parts + RoundParts / 2,
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Hi = getCopyFromParts(DAG, dl, Parts + RoundParts / 2,
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RoundParts / 2, PartVT, HalfVT);
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} else {
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Lo = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[0]);
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@ -223,7 +223,7 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl, unsigned Order,
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// Assemble the trailing non-power-of-2 part.
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unsigned OddParts = NumParts - RoundParts;
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EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
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Hi = getCopyFromParts(DAG, dl, Order,
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Hi = getCopyFromParts(DAG, dl,
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Parts + RoundParts, OddParts, PartVT, OddVT);
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// Combine the round and odd parts.
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@ -259,7 +259,7 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl, unsigned Order,
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// If the register was not expanded, truncate or copy the value,
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// as appropriate.
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for (unsigned i = 0; i != NumParts; ++i)
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Ops[i] = getCopyFromParts(DAG, dl, Order, &Parts[i], 1,
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Ops[i] = getCopyFromParts(DAG, dl, &Parts[i], 1,
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PartVT, IntermediateVT);
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} else if (NumParts > 0) {
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// If the intermediate type was expanded, build the intermediate
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@ -268,7 +268,7 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl, unsigned Order,
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"Must expand into a divisible number of parts!");
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unsigned Factor = NumParts / NumIntermediates;
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for (unsigned i = 0; i != NumIntermediates; ++i)
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Ops[i] = getCopyFromParts(DAG, dl, Order, &Parts[i * Factor], Factor,
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Ops[i] = getCopyFromParts(DAG, dl, &Parts[i * Factor], Factor,
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PartVT, IntermediateVT);
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}
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@ -292,7 +292,7 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl, unsigned Order,
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assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
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!PartVT.isVector() && "Unexpected split");
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EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
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Val = getCopyFromParts(DAG, dl, Order, Parts, NumParts, PartVT, IntVT);
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Val = getCopyFromParts(DAG, dl, Parts, NumParts, PartVT, IntVT);
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}
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}
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@ -349,7 +349,7 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl, unsigned Order,
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/// getCopyToParts - Create a series of nodes that contain the specified value
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/// split into legal parts. If the parts contain more bits than Val, then, for
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/// integers, ExtendKind can be used to specify how to generate the extra bits.
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static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, unsigned Order,
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static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl,
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SDValue Val, SDValue *Parts, unsigned NumParts,
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EVT PartVT,
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ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
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@ -417,7 +417,7 @@ static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, unsigned Order,
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SDValue OddVal = DAG.getNode(ISD::SRL, dl, ValueVT, Val,
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DAG.getConstant(RoundBits,
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TLI.getPointerTy()));
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getCopyToParts(DAG, dl, Order, OddVal, Parts + RoundParts,
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getCopyToParts(DAG, dl, OddVal, Parts + RoundParts,
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OddParts, PartVT);
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if (TLI.isBigEndian())
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@ -514,7 +514,7 @@ static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, unsigned Order,
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// If the register was not expanded, promote or copy the value,
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// as appropriate.
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for (unsigned i = 0; i != NumParts; ++i)
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getCopyToParts(DAG, dl, Order, Ops[i], &Parts[i], 1, PartVT);
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getCopyToParts(DAG, dl, Ops[i], &Parts[i], 1, PartVT);
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} else if (NumParts > 0) {
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// If the intermediate type was expanded, split each the value into
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// legal parts.
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"Must expand into a divisible number of parts!");
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unsigned Factor = NumParts / NumIntermediates;
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for (unsigned i = 0; i != NumIntermediates; ++i)
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getCopyToParts(DAG, dl, Order, Ops[i], &Parts[i*Factor], Factor, PartVT);
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getCopyToParts(DAG, dl, Ops[i], &Parts[i*Factor], Factor, PartVT);
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}
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}
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@ -747,8 +747,7 @@ SDValue SelectionDAGBuilder::getValue(const Value *V) {
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RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
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SDValue Chain = DAG.getEntryNode();
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return RFV.getCopyFromRegs(DAG, getCurDebugLoc(),
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SDNodeOrder, Chain, NULL);
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return RFV.getCopyFromRegs(DAG, getCurDebugLoc(), Chain, NULL);
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}
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/// Get the EVTs and ArgFlags collections that represent the legalized return
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@ -879,7 +878,7 @@ void SelectionDAGBuilder::visitRet(ReturnInst &I) {
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unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
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EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
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SmallVector<SDValue, 4> Parts(NumParts);
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getCopyToParts(DAG, getCurDebugLoc(), SDNodeOrder,
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getCopyToParts(DAG, getCurDebugLoc(),
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SDValue(RetOp.getNode(), RetOp.getResNo() + j),
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&Parts[0], NumParts, PartVT, ExtendKind);
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@ -2888,7 +2887,7 @@ void SelectionDAGBuilder::visitTargetIntrinsic(CallInst &I,
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///
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/// where Op is the hexidecimal representation of floating point value.
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static SDValue
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GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl, unsigned Order) {
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GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
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SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
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DAG.getConstant(0x007fffff, MVT::i32));
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SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
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@ -2903,7 +2902,7 @@ GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl, unsigned Order) {
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/// where Op is the hexidecimal representation of floating point value.
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static SDValue
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GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
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DebugLoc dl, unsigned Order) {
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DebugLoc dl) {
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SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
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DAG.getConstant(0x7f800000, MVT::i32));
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SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
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@ -3087,13 +3086,13 @@ SelectionDAGBuilder::visitLog(CallInst &I) {
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SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
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// Scale the exponent by log(2) [0.69314718f].
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SDValue Exp = GetExponent(DAG, Op1, TLI, dl, SDNodeOrder);
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SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
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SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
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getF32Constant(DAG, 0x3f317218));
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// Get the significand and build it into a floating-point number with
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// exponent of 1.
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SDValue X = GetSignificand(DAG, Op1, dl, SDNodeOrder);
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SDValue X = GetSignificand(DAG, Op1, dl);
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if (LimitFloatPrecision <= 6) {
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// For floating-point precision of 6:
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@ -3197,11 +3196,11 @@ SelectionDAGBuilder::visitLog2(CallInst &I) {
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SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
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// Get the exponent.
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SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl, SDNodeOrder);
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SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
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// Get the significand and build it into a floating-point number with
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// exponent of 1.
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SDValue X = GetSignificand(DAG, Op1, dl, SDNodeOrder);
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SDValue X = GetSignificand(DAG, Op1, dl);
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// Different possible minimax approximations of significand in
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// floating-point for various degrees of accuracy over [1,2].
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@ -3306,13 +3305,13 @@ SelectionDAGBuilder::visitLog10(CallInst &I) {
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SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
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// Scale the exponent by log10(2) [0.30102999f].
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SDValue Exp = GetExponent(DAG, Op1, TLI, dl, SDNodeOrder);
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SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
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SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
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getF32Constant(DAG, 0x3e9a209a));
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// Get the significand and build it into a floating-point number with
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// exponent of 1.
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SDValue X = GetSignificand(DAG, Op1, dl, SDNodeOrder);
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SDValue X = GetSignificand(DAG, Op1, dl);
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if (LimitFloatPrecision <= 6) {
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// For floating-point precision of 6:
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@ -4394,7 +4393,7 @@ void SelectionDAGBuilder::LowerCallTo(CallSite CS, SDValue Callee,
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CS.getCallingConv(),
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isTailCall,
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!CS.getInstruction()->use_empty(),
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Callee, Args, DAG, getCurDebugLoc(), SDNodeOrder);
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Callee, Args, DAG, getCurDebugLoc());
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assert((isTailCall || Result.second.getNode()) &&
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"Non-null chain expected with non-tail call!");
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assert((Result.second.getNode() || !Result.first.getNode()) &&
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@ -4442,7 +4441,7 @@ void SelectionDAGBuilder::LowerCallTo(CallSite CS, SDValue Callee,
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unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT);
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SDValue ReturnValue =
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getCopyFromParts(DAG, getCurDebugLoc(), SDNodeOrder, &Values[CurReg], NumRegs,
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getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs,
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RegisterVT, VT, AssertOp);
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ReturnValues.push_back(ReturnValue);
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CurReg += NumRegs;
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@ -4709,8 +4708,7 @@ void SelectionDAGBuilder::visitCall(CallInst &I) {
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/// Chain/Flag as the input and updates them for the output Chain/Flag.
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/// If the Flag pointer is NULL, no flag is used.
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SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
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unsigned Order, SDValue &Chain,
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SDValue *Flag) const {
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SDValue &Chain, SDValue *Flag) const {
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// Assemble the legal parts into the final values.
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SmallVector<SDValue, 4> Values(ValueVTs.size());
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SmallVector<SDValue, 8> Parts;
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@ -4775,7 +4773,7 @@ SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
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Parts[i] = P;
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}
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Values[Value] = getCopyFromParts(DAG, dl, Order, Parts.begin(),
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Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
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NumRegs, RegisterVT, ValueVT);
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Part += NumRegs;
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Parts.clear();
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@ -4791,8 +4789,7 @@ SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
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/// Chain/Flag as the input and updates them for the output Chain/Flag.
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/// If the Flag pointer is NULL, no flag is used.
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void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
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unsigned Order, SDValue &Chain,
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SDValue *Flag) const {
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SDValue &Chain, SDValue *Flag) const {
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// Get the list of the values's legal parts.
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unsigned NumRegs = Regs.size();
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SmallVector<SDValue, 8> Parts(NumRegs);
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@ -4801,7 +4798,7 @@ void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
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unsigned NumParts = TLI->getNumRegisters(*DAG.getContext(), ValueVT);
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EVT RegisterVT = RegVTs[Value];
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getCopyToParts(DAG, dl, Order,
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getCopyToParts(DAG, dl,
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Val.getValue(Val.getResNo() + Value),
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&Parts[Part], NumParts, RegisterVT);
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Part += NumParts;
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@ -4842,7 +4839,7 @@ void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
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/// values added into it.
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void RegsForValue::AddInlineAsmOperands(unsigned Code,
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bool HasMatching,unsigned MatchingIdx,
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SelectionDAG &DAG, unsigned Order,
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SelectionDAG &DAG,
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std::vector<SDValue> &Ops) const {
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assert(Regs.size() < (1 << 13) && "Too many inline asm outputs!");
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unsigned Flag = Code | (Regs.size() << 3);
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@ -5432,7 +5429,7 @@ void SelectionDAGBuilder::visitInlineAsm(CallSite CS) {
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2 /* REGDEF */ ,
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false,
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0,
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DAG, SDNodeOrder,
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DAG,
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AsmNodeOperands);
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break;
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}
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@ -5480,10 +5477,10 @@ void SelectionDAGBuilder::visitInlineAsm(CallSite CS) {
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// Use the produced MatchedRegs object to
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MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
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SDNodeOrder, Chain, &Flag);
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Chain, &Flag);
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MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/,
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true, OpInfo.getMatchedOperand(),
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DAG, SDNodeOrder, AsmNodeOperands);
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DAG, AsmNodeOperands);
|
||||
break;
|
||||
} else {
|
||||
assert(((OpFlag & 7) == 4) && "Unknown matching constraint!");
|
||||
|
@ -5544,11 +5541,10 @@ void SelectionDAGBuilder::visitInlineAsm(CallSite CS) {
|
|||
}
|
||||
|
||||
OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
|
||||
SDNodeOrder, Chain, &Flag);
|
||||
Chain, &Flag);
|
||||
|
||||
OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, false, 0,
|
||||
DAG, SDNodeOrder,
|
||||
AsmNodeOperands);
|
||||
DAG, AsmNodeOperands);
|
||||
break;
|
||||
}
|
||||
case InlineAsm::isClobber: {
|
||||
|
@ -5556,7 +5552,7 @@ void SelectionDAGBuilder::visitInlineAsm(CallSite CS) {
|
|||
// allocator is aware that the physreg got clobbered.
|
||||
if (!OpInfo.AssignedRegs.Regs.empty())
|
||||
OpInfo.AssignedRegs.AddInlineAsmOperands(6 /* EARLYCLOBBER REGDEF */,
|
||||
false, 0, DAG, SDNodeOrder,
|
||||
false, 0, DAG,
|
||||
AsmNodeOperands);
|
||||
break;
|
||||
}
|
||||
|
@ -5576,7 +5572,7 @@ void SelectionDAGBuilder::visitInlineAsm(CallSite CS) {
|
|||
// and set it as the value of the call.
|
||||
if (!RetValRegs.Regs.empty()) {
|
||||
SDValue Val = RetValRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
|
||||
SDNodeOrder, Chain, &Flag);
|
||||
Chain, &Flag);
|
||||
|
||||
// FIXME: Why don't we do this for inline asms with MRVs?
|
||||
if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
|
||||
|
@ -5616,7 +5612,7 @@ void SelectionDAGBuilder::visitInlineAsm(CallSite CS) {
|
|||
RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
|
||||
Value *Ptr = IndirectStoresToEmit[i].second;
|
||||
SDValue OutVal = OutRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
|
||||
SDNodeOrder, Chain, &Flag);
|
||||
Chain, &Flag);
|
||||
StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
|
||||
|
||||
}
|
||||
|
@ -5681,8 +5677,7 @@ TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
|
|||
CallingConv::ID CallConv, bool isTailCall,
|
||||
bool isReturnValueUsed,
|
||||
SDValue Callee,
|
||||
ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl,
|
||||
unsigned Order) {
|
||||
ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl) {
|
||||
// Handle all of the outgoing arguments.
|
||||
SmallVector<ISD::OutputArg, 32> Outs;
|
||||
for (unsigned i = 0, e = Args.size(); i != e; ++i) {
|
||||
|
@ -5733,7 +5728,7 @@ TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
|
|||
else if (Args[i].isZExt)
|
||||
ExtendKind = ISD::ZERO_EXTEND;
|
||||
|
||||
getCopyToParts(DAG, dl, Order, Op, &Parts[0], NumParts,
|
||||
getCopyToParts(DAG, dl, Op, &Parts[0], NumParts,
|
||||
PartVT, ExtendKind);
|
||||
|
||||
for (unsigned j = 0; j != NumParts; ++j) {
|
||||
|
@ -5812,7 +5807,7 @@ TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
|
|||
EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
|
||||
unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
|
||||
|
||||
ReturnValues.push_back(getCopyFromParts(DAG, dl, Order, &InVals[CurReg],
|
||||
ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg],
|
||||
NumRegs, RegisterVT, VT,
|
||||
AssertOp));
|
||||
CurReg += NumRegs;
|
||||
|
@ -5852,7 +5847,7 @@ void SelectionDAGBuilder::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
|
|||
|
||||
RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
|
||||
SDValue Chain = DAG.getEntryNode();
|
||||
RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), SDNodeOrder, Chain, 0);
|
||||
RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
|
||||
PendingExports.push_back(Chain);
|
||||
}
|
||||
|
||||
|
@ -5978,7 +5973,7 @@ void SelectionDAGISel::LowerArguments(BasicBlock *LLVMBB) {
|
|||
EVT VT = ValueVTs[0];
|
||||
EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
|
||||
ISD::NodeType AssertOp = ISD::DELETED_NODE;
|
||||
SDValue ArgValue = getCopyFromParts(DAG, dl, 0, &InVals[0], 1,
|
||||
SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
|
||||
RegVT, VT, AssertOp);
|
||||
|
||||
MachineFunction& MF = SDB->DAG.getMachineFunction();
|
||||
|
@ -6012,7 +6007,7 @@ void SelectionDAGISel::LowerArguments(BasicBlock *LLVMBB) {
|
|||
else if (F.paramHasAttr(Idx, Attribute::ZExt))
|
||||
AssertOp = ISD::AssertZext;
|
||||
|
||||
ArgValues.push_back(getCopyFromParts(DAG, dl, 0, &InVals[i],
|
||||
ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
|
||||
NumParts, PartVT, VT,
|
||||
AssertOp));
|
||||
}
|
||||
|
|
|
@ -1282,8 +1282,7 @@ ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
|
|||
LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()),
|
||||
false, false, false, false,
|
||||
0, CallingConv::C, false, /*isReturnValueUsed=*/true,
|
||||
DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl,
|
||||
DAG.GetOrdering(Chain.getNode()));
|
||||
DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
|
||||
return CallResult.first;
|
||||
}
|
||||
|
||||
|
|
|
@ -118,8 +118,7 @@ namespace {
|
|||
TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
|
||||
0, TLI.getLibcallCallingConv(LC), false,
|
||||
/*isReturnValueUsed=*/true,
|
||||
Callee, Args, DAG, Op.getDebugLoc(),
|
||||
DAG.GetOrdering(InChain.getNode()));
|
||||
Callee, Args, DAG, Op.getDebugLoc());
|
||||
|
||||
return CallInfo.first;
|
||||
}
|
||||
|
|
|
@ -419,8 +419,7 @@ PIC16TargetLowering::MakePIC16Libcall(PIC16ISD::PIC16Libcall Call,
|
|||
LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
|
||||
false, 0, CallingConv::C, false,
|
||||
/*isReturnValueUsed=*/true,
|
||||
Callee, Args, DAG, dl,
|
||||
DAG.GetOrdering(DAG.getEntryNode().getNode()));
|
||||
Callee, Args, DAG, dl);
|
||||
|
||||
return CallInfo.first;
|
||||
}
|
||||
|
|
|
@ -1334,7 +1334,7 @@ SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
|
|||
false, false, false, false, 0, CallingConv::C, false,
|
||||
/*isReturnValueUsed=*/true,
|
||||
DAG.getExternalSymbol("__trampoline_setup", PtrVT),
|
||||
Args, DAG, dl, DAG.GetOrdering(Chain.getNode()));
|
||||
Args, DAG, dl);
|
||||
|
||||
SDValue Ops[] =
|
||||
{ CallResult.first, CallResult.second };
|
||||
|
|
|
@ -6474,8 +6474,7 @@ X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
|
|||
LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()),
|
||||
false, false, false, false,
|
||||
0, CallingConv::C, false, /*isReturnValueUsed=*/false,
|
||||
DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl,
|
||||
DAG.GetOrdering(Chain.getNode()));
|
||||
DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl);
|
||||
return CallResult.second;
|
||||
}
|
||||
|
||||
|
|
|
@ -473,7 +473,7 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG)
|
|||
false, false, 0, CallingConv::C, false,
|
||||
/*isReturnValueUsed=*/true,
|
||||
DAG.getExternalSymbol("__misaligned_load", getPointerTy()),
|
||||
Args, DAG, dl, DAG.GetOrdering(Chain.getNode()));
|
||||
Args, DAG, dl);
|
||||
|
||||
SDValue Ops[] =
|
||||
{ CallResult.first, CallResult.second };
|
||||
|
@ -536,7 +536,7 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG)
|
|||
false, false, 0, CallingConv::C, false,
|
||||
/*isReturnValueUsed=*/true,
|
||||
DAG.getExternalSymbol("__misaligned_store", getPointerTy()),
|
||||
Args, DAG, dl, DAG.GetOrdering(Chain.getNode()));
|
||||
Args, DAG, dl);
|
||||
|
||||
return CallResult.second;
|
||||
}
|
||||
|
|
Loading…
Reference in New Issue