forked from OSchip/llvm-project
Revert r163761 "Don't fold indexed loads into TCRETURNmi64."
The patch caused "Wrong topological sorting" assertions. llvm-svn: 163810
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@ -204,9 +204,6 @@ namespace {
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bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
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SDValue &Scale, SDValue &Index, SDValue &Disp,
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SDValue &Segment);
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bool SelectSingleRegAddr(SDNode *Parent, SDValue N, SDValue &Base,
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SDValue &Scale, SDValue &Index, SDValue &Disp,
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SDValue &Segment);
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bool SelectLEAAddr(SDValue N, SDValue &Base,
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SDValue &Scale, SDValue &Index, SDValue &Disp,
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SDValue &Segment);
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@ -1322,31 +1319,6 @@ bool X86DAGToDAGISel::SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
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return true;
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}
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/// SelectSingleRegAddr - Like SelectAddr, but reject any address that would
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/// require more than one allocatable register.
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///
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/// This is used for a TCRETURNmi64 instruction when used to tail call a
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/// variadic function with 6 arguments: Only %r11 is available from GR64_TC.
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/// The other scratch register, %rax, is needed to pass in the number of vector
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/// registers used in the variadic arguments.
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///
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bool X86DAGToDAGISel::SelectSingleRegAddr(SDNode *Parent, SDValue N,
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SDValue &Base,
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SDValue &Scale, SDValue &Index,
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SDValue &Disp, SDValue &Segment) {
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if (!SelectAddr(Parent, N, Base, Scale, Index, Disp, Segment))
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return false;
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// Anything %RIP relative is fine.
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if (RegisterSDNode *Reg = dyn_cast<RegisterSDNode>(Base))
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if (Reg->getReg() == X86::RIP)
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return true;
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// Check that the index register is 0.
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if (RegisterSDNode *Reg = dyn_cast<RegisterSDNode>(Index))
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if (Reg->getReg() == 0)
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return true;
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return false;
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}
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/// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
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/// match a load whose top elements are either undef or zeros. The load flavor
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/// is derived from the type of N, which is either v4f32 or v2f64.
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@ -1041,13 +1041,7 @@ def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
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(TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>,
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Requires<[In64BitMode]>;
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// When calling a variadic function with 6 arguments, 7 scratch registers are
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// needed since %al holds the number of vector registers used. That leaves %r11
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// as the only remaining GR64_TC register for the addressing mode.
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//
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// The single_reg_addr pattern rejects any addressing modes that would need
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// more than one register.
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def : Pat<(X86tcret (load single_reg_addr:$dst), imm:$off),
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def : Pat<(X86tcret (load addr:$dst), imm:$off),
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(TCRETURNmi64 addr:$dst, imm:$off)>,
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Requires<[In64BitMode]>;
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@ -543,10 +543,6 @@ def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
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def tls64baseaddr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
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[tglobaltlsaddr], []>;
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// Same as addr, but reject addressing modes requiring more than one register.
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def single_reg_addr : ComplexPattern<iPTR, 5, "SelectSingleRegAddr", [],
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[SDNPWantParent]>;
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//===----------------------------------------------------------------------===//
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// X86 Instruction Predicate Definitions.
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def HasCMov : Predicate<"Subtarget->hasCMov()">;
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@ -1,4 +1,4 @@
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; RUN: llc < %s -verify-machineinstrs | FileCheck %s
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; RUN: llc < %s | FileCheck %s
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target datalayout = "e-p:64:64:64-S128-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f16:16:16-f32:32:32-f64:64:64-f128:128:128-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
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target triple = "x86_64-apple-darwin11.4.0"
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@ -93,38 +93,4 @@ define { i64, i64 } @crash(i8* %this) {
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ret { i64, i64 } %mrv7
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}
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; <rdar://problem/12282281> Fold an indexed load into the tail call instruction.
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; Calling a varargs function with 6 arguments requires 7 registers (%al is the
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; vector count for varargs functions). This leaves %r11 as the only available
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; scratch register.
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;
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; It is not possible to fold an indexed load into TCRETURNmi64 in that case.
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;
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; typedef int (*funcptr)(void*, ...);
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; extern const funcptr funcs[];
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; int f(int n) {
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; return funcs[n](0, 0, 0, 0, 0, 0);
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; }
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;
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; CHECK: rdar12282281
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; CHECK: jmpq *%r11 # TAILCALL
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@funcs = external constant [0 x i32 (i8*, ...)*]
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define i32 @rdar12282281(i32 %n) nounwind uwtable ssp {
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entry:
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%idxprom = sext i32 %n to i64
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%arrayidx = getelementptr inbounds [0 x i32 (i8*, ...)*]* @funcs, i64 0, i64 %idxprom
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%0 = load i32 (i8*, ...)** %arrayidx, align 8
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%call = tail call i32 (i8*, ...)* %0(i8* null, i32 0, i32 0, i32 0, i32 0, i32 0) nounwind
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ret i32 %call
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}
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; Same thing, using a fixed offset. The load should foid.
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; CHECK: rdar12282281fixed
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; CHECK: jmpq *8(%r11) # TAILCALL
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define i32 @rdar12282281fixed() nounwind uwtable ssp {
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entry:
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%0 = load i32 (i8*, ...)** getelementptr inbounds ([0 x i32 (i8*, ...)*]* @funcs, i64 0, i64 1), align 8
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%call.i = tail call i32 (i8*, ...)* %0(i8* null, i32 0, i32 0, i32 0, i32 0, i32 0) nounwind
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ret i32 %call.i
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}
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