forked from OSchip/llvm-project
[AArch64] Add TableGen patterns to generate uaddlv
uaddv(uaddlp(x)) ==> uaddlv(x) addp(uaddlp(x)) ==> uaddlv(x) Differential Revision: https://reviews.llvm.org/D104236
This commit is contained in:
Jingu Kang
parent
836992ab9a
commit
78b75b452b
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@ -5653,6 +5653,25 @@ defm FMAXV : SIMDFPAcrossLanes<0b01111, 0, "fmaxv", int_aarch64_neon_fmaxv>;
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defm FMINNMV : SIMDFPAcrossLanes<0b01100, 1, "fminnmv", int_aarch64_neon_fminnmv>;
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defm FMINV : SIMDFPAcrossLanes<0b01111, 1, "fminv", int_aarch64_neon_fminv>;
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// Patterns for uaddv(uaddlp(x)) ==> uaddlv
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def : Pat<(i32 (vector_extract (v8i16 (insert_subvector undef,
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(v4i16 (AArch64uaddv (v4i16 (AArch64uaddlp (v8i8 V64:$op))))),
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(i64 0))), (i64 0))),
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(EXTRACT_SUBREG (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
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(UADDLVv4i16v V64:$op), ssub), ssub)>;
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def : Pat<(i32 (vector_extract (v8i16 (AArch64uaddv (v8i16 (AArch64uaddlp
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(v16i8 V128:$op))))), (i64 0))),
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(EXTRACT_SUBREG (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
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(UADDLVv16i8v V128:$op), hsub), ssub)>;
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def : Pat<(v4i32 (AArch64uaddv (v4i32 (AArch64uaddlp (v8i16 V128:$op))))),
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(INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), (UADDLVv8i16v V128:$op), ssub)>;
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// Patterns for addp(uaddlp(x))) ==> uaddlv
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def : Pat<(v2i32 (AArch64uaddv (v2i32 (AArch64uaddlp (v4i16 V64:$op))))),
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(INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), (UADDLVv4i16v V64:$op), ssub)>;
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def : Pat<(v2i64 (AArch64uaddv (v2i64 (AArch64uaddlp (v4i32 V128:$op))))),
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(INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (UADDLVv4i32v V128:$op), dsub)>;
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// Patterns for across-vector intrinsics, that have a node equivalent, that
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// returns a vector (with only the low lane defined) instead of a scalar.
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// In effect, opNode is the same as (scalar_to_vector (IntNode)).
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@ -220,8 +220,7 @@ define i32 @uabd16b_rdx_i32(<16 x i8> %a, <16 x i8> %b) {
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; CHECK: // %bb.0:
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; CHECK-NEXT: uabdl.8h v2, v0, v1
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; CHECK-NEXT: uabal2.8h v2, v0, v1
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; CHECK-NEXT: uaddlp.4s v0, v2
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; CHECK-NEXT: addv.4s s0, v0
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; CHECK-NEXT: uaddlv.8h s0, v2
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%aext = zext <16 x i8> %a to <16 x i32>
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@ -239,8 +238,7 @@ define i32 @sabd16b_rdx_i32(<16 x i8> %a, <16 x i8> %b) {
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; CHECK: // %bb.0:
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; CHECK-NEXT: sabdl.8h v2, v0, v1
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; CHECK-NEXT: sabal2.8h v2, v0, v1
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; CHECK-NEXT: uaddlp.4s v0, v2
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; CHECK-NEXT: addv.4s s0, v0
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; CHECK-NEXT: uaddlv.8h s0, v2
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%aext = sext <16 x i8> %a to <16 x i32>
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@ -11,8 +11,7 @@ define i32 @test_sad_v16i8_zext(i8* nocapture readonly %a, i8* nocapture readonl
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; CHECK-NEXT: ldr q1, [x1]
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; CHECK-NEXT: uabdl v2.8h, v1.8b, v0.8b
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; CHECK-NEXT: uabal2 v2.8h, v1.16b, v0.16b
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; CHECK-NEXT: uaddlp v0.4s, v2.8h
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; CHECK-NEXT: addv s0, v0.4s
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; CHECK-NEXT: uaddlv s0, v2.8h
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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entry:
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@ -35,8 +34,7 @@ define i32 @test_sad_v16i8_sext(i8* nocapture readonly %a, i8* nocapture readonl
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; CHECK-NEXT: ldr q1, [x1]
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; CHECK-NEXT: sabdl v2.8h, v1.8b, v0.8b
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; CHECK-NEXT: sabal2 v2.8h, v1.16b, v0.16b
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; CHECK-NEXT: uaddlp v0.4s, v2.8h
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; CHECK-NEXT: addv s0, v0.4s
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; CHECK-NEXT: uaddlv s0, v2.8h
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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entry:
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@ -0,0 +1,79 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple aarch64-none-linux-gnu < %s | FileCheck %s
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declare <4 x i16> @llvm.aarch64.neon.uaddlp.v4i16.v8i8(<8 x i8>) nounwind readnone
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declare <8 x i16> @llvm.aarch64.neon.uaddlp.v8i16.v16i8(<16 x i8>) nounwind readnone
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declare <4 x i32> @llvm.aarch64.neon.uaddlp.v4i32.v8i16(<8 x i16>) nounwind readnone
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declare <2 x i64> @llvm.aarch64.neon.uaddlp.v2i64.v4i32(<4 x i32>) nounwind readnone
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declare <2 x i32> @llvm.aarch64.neon.uaddlp.v2i32.v4i16(<4 x i16>) nounwind readnone
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declare i16 @llvm.vector.reduce.add.v4i16(<4 x i16>) nounwind readnone
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declare i16 @llvm.vector.reduce.add.v8i16(<8 x i16>) nounwind readnone
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declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>) nounwind readnone
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declare i64 @llvm.vector.reduce.add.v2i64(<2 x i64>) nounwind readnone
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declare i32 @llvm.vector.reduce.add.v2i32(<2 x i32>) nounwind readnone
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define i16 @uaddlv4h_from_v8i8(<8 x i8>* %A) nounwind {
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; CHECK-LABEL: uaddlv4h_from_v8i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr d0, [x0]
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; CHECK-NEXT: uaddlv s0, v0.4h
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp3 = call <4 x i16> @llvm.aarch64.neon.uaddlp.v4i16.v8i8(<8 x i8> %tmp1)
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%tmp5 = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> %tmp3)
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ret i16 %tmp5
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}
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define i16 @uaddlv16b_from_v16i8(<16 x i8>* %A) nounwind {
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; CHECK-LABEL: uaddlv16b_from_v16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: uaddlv h0, v0.16b
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%tmp1 = load <16 x i8>, <16 x i8>* %A
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%tmp3 = call <8 x i16> @llvm.aarch64.neon.uaddlp.v8i16.v16i8(<16 x i8> %tmp1)
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%tmp5 = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %tmp3)
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ret i16 %tmp5
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}
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define i32 @uaddlv8h_from_v8i16(<8 x i16>* %A) nounwind {
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; CHECK-LABEL: uaddlv8h_from_v8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: uaddlv s0, v0.8h
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%tmp1 = load <8 x i16>, <8 x i16>* %A
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%tmp3 = call <4 x i32> @llvm.aarch64.neon.uaddlp.v4i32.v8i16(<8 x i16> %tmp1)
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%tmp5 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %tmp3)
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ret i32 %tmp5
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}
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define i64 @uaddlv4s_from_v4i32(<4 x i32>* %A) nounwind {
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; CHECK-LABEL: uaddlv4s_from_v4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: uaddlv d0, v0.4s
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; CHECK-NEXT: fmov x0, d0
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; CHECK-NEXT: ret
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%tmp1 = load <4 x i32>, <4 x i32>* %A
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%tmp3 = call <2 x i64> @llvm.aarch64.neon.uaddlp.v2i64.v4i32(<4 x i32> %tmp1)
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%tmp5 = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %tmp3)
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ret i64 %tmp5
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}
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define i32 @uaddlv4h_from_v4i16(<4 x i16>* %A) nounwind {
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; CHECK-LABEL: uaddlv4h_from_v4i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr d0, [x0]
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; CHECK-NEXT: uaddlv s0, v0.4h
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp3 = call <2 x i32> @llvm.aarch64.neon.uaddlp.v2i32.v4i16(<4 x i16> %tmp1)
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%tmp5 = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> %tmp3)
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ret i32 %tmp5
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}
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