forked from OSchip/llvm-project
[ARM] Use ProcResGroup in Cortex-M7 scheduling model
Used to model structural hazards on FP issue, where some instructions take up 2 issue slots and others one as well as similar structural hazards on load issue, where some instructions take up two load lanes and others one. Differential Revision: https://reviews.llvm.org/D98977
This commit is contained in:
David Penry
David Green
parent
3c54762226
commit
78a871abf7
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@ -19,6 +19,8 @@ def CortexM7Model : SchedMachineModel {
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let CompleteModel = 0;
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}
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let SchedModel = CortexM7Model in {
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//===--------------------------------------------------------------------===//
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// The Cortex-M7 has two ALU, two LOAD, a STORE, a MAC, a BRANCH and a VFP
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// pipe. The stages relevant to scheduling are as follows:
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@ -33,7 +35,9 @@ def CortexM7Model : SchedMachineModel {
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// for scheduling, so simple ALU operations executing in EX2 will have
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// ReadAdvance<0> (the default) for their source operands and Latency = 1.
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def M7UnitLoad : ProcResource<2> { let BufferSize = 0; }
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def M7UnitLoadL : ProcResource<1> { let BufferSize = 0; }
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def M7UnitLoadH : ProcResource<1> { let BufferSize = 0; }
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def M7UnitLoad : ProcResGroup<[M7UnitLoadL,M7UnitLoadH]> { let BufferSize = 0; }
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def M7UnitStore : ProcResource<1> { let BufferSize = 0; }
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def M7UnitALU : ProcResource<2>;
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def M7UnitShift1 : ProcResource<1> { let BufferSize = 0; }
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@ -41,14 +45,14 @@ def M7UnitShift2 : ProcResource<1> { let BufferSize = 0; }
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def M7UnitMAC : ProcResource<1> { let BufferSize = 0; }
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def M7UnitBranch : ProcResource<1> { let BufferSize = 0; }
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def M7UnitVFP : ProcResource<1> { let BufferSize = 0; }
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def M7UnitVPort : ProcResource<2> { let BufferSize = 0; }
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def M7UnitVPortL : ProcResource<1> { let BufferSize = 0; }
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def M7UnitVPortH : ProcResource<1> { let BufferSize = 0; }
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def M7UnitVPort : ProcResGroup<[M7UnitVPortL,M7UnitVPortH]> { let BufferSize = 0; }
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def M7UnitSIMD : ProcResource<1> { let BufferSize = 0; }
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//===---------------------------------------------------------------------===//
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// Subtarget-specific SchedWrite types with map ProcResources and set latency.
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let SchedModel = CortexM7Model in {
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def : WriteRes<WriteALU, [M7UnitALU]> { let Latency = 1; }
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// Basic ALU with shifts.
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@ -105,39 +109,42 @@ def : WriteRes<WriteNoop, []> { let Latency = 0; }
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// Floating point conversions.
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def : WriteRes<WriteFPCVT, [M7UnitVFP, M7UnitVPort]> { let Latency = 3; }
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def : WriteRes<WriteFPMOV, [M7UnitVPort]> { let Latency = 3; }
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def M7WriteFPMOV64 : SchedWriteRes<[M7UnitVPortL, M7UnitVPortH]> {
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let Latency = 3;
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}
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// The FP pipeline has a latency of 3 cycles.
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// ALU operations (32/64-bit). These go down the FP pipeline.
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def : WriteRes<WriteFPALU32, [M7UnitVFP, M7UnitVPort]> { let Latency = 3; }
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def : WriteRes<WriteFPALU64, [M7UnitVFP, M7UnitVPort, M7UnitVPort]> {
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def : WriteRes<WriteFPALU64, [M7UnitVFP, M7UnitVPortL, M7UnitVPortH]> {
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let Latency = 4;
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let BeginGroup = 1;
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}
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// Multiplication
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def : WriteRes<WriteFPMUL32, [M7UnitVFP, M7UnitVPort]> { let Latency = 3; }
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def : WriteRes<WriteFPMUL64, [M7UnitVFP, M7UnitVPort, M7UnitVPort]> {
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def : WriteRes<WriteFPMUL64, [M7UnitVFP, M7UnitVPortL, M7UnitVPortH]> {
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let Latency = 7;
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let BeginGroup = 1;
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}
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// Multiply-accumulate. FPMAC goes down the FP Pipeline.
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def : WriteRes<WriteFPMAC32, [M7UnitVFP, M7UnitVPort]> { let Latency = 6; }
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def : WriteRes<WriteFPMAC64, [M7UnitVFP, M7UnitVPort, M7UnitVPort]> {
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def : WriteRes<WriteFPMAC64, [M7UnitVFP, M7UnitVPortL, M7UnitVPortH]> {
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let Latency = 11;
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let BeginGroup = 1;
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}
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// Division. Effective scheduling latency is 3, though real latency is larger
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def : WriteRes<WriteFPDIV32, [M7UnitVFP, M7UnitVPort]> { let Latency = 16; }
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def : WriteRes<WriteFPDIV64, [M7UnitVFP, M7UnitVPort, M7UnitVPort]> {
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def : WriteRes<WriteFPDIV64, [M7UnitVFP, M7UnitVPortL, M7UnitVPortH]> {
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let Latency = 30;
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let BeginGroup = 1;
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}
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// Square-root. Effective scheduling latency is 3; real latency is larger
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def : WriteRes<WriteFPSQRT32, [M7UnitVFP, M7UnitVPort]> { let Latency = 16; }
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def : WriteRes<WriteFPSQRT64, [M7UnitVFP, M7UnitVPort, M7UnitVPort]> {
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def : WriteRes<WriteFPSQRT64, [M7UnitVFP, M7UnitVPortL, M7UnitVPortH]> {
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let Latency = 30;
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let BeginGroup = 1;
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}
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@ -283,12 +290,12 @@ def : InstRW<[M7TableLoad, M7Read_ISS, M7Read_ISS], (instregex "t2TB")>;
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// VFP loads and stores
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def M7LoadSP : SchedWriteRes<[M7UnitLoad, M7UnitVPort]> { let Latency = 1; }
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def M7LoadDP : SchedWriteRes<[M7UnitLoad, M7UnitVPort, M7UnitVPort]> {
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def M7LoadDP : SchedWriteRes<[M7UnitLoadL, M7UnitLoadH, M7UnitVPortL, M7UnitVPortH]> {
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let Latency = 2;
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let SingleIssue = 1;
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}
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def M7StoreSP : SchedWriteRes<[M7UnitStore, M7UnitVPort]>;
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def M7StoreDP : SchedWriteRes<[M7UnitStore, M7UnitVPort, M7UnitVPort]> {
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def M7StoreDP : SchedWriteRes<[M7UnitStore, M7UnitVPortL, M7UnitVPortH]> {
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let SingleIssue = 1;
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}
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@ -0,0 +1,39 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple arm-arm-eabi -mcpu=cortex-m7 -verify-machineinstrs -run-pass=postmisched %s -o - | FileCheck %s
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---
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name: test_groups
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alignment: 2
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tracksRegLiveness: true
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liveins:
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- { reg: '$d0' }
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- { reg: '$r0' }
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- { reg: '$r1' }
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- { reg: '$r2' }
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- { reg: '$r3' }
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- { reg: '$r4' }
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frameInfo:
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maxAlignment: 1
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maxCallFrameSize: 0
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0, $r0, $r1, $r2, $r3, $r4
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; CHECK-LABEL: name: test_groups
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; CHECK: liveins: $d0, $r0, $r1, $r2, $r3, $r4
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; CHECK: renamable $d0 = VADDD killed renamable $d0, renamable $d0, 14 /* CC::al */, $noreg
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; CHECK: renamable $s2 = VLDRS killed renamable $r0, 0, 14 /* CC::al */, $noreg
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; CHECK: VSTRS killed renamable $s2, killed renamable $r1, 0, 14 /* CC::al */, $noreg
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; CHECK: renamable $r3 = t2ADDrr killed renamable $r3, renamable $r3, 14 /* CC::al */, $noreg, $noreg
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; CHECK: t2STRi12 killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg
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; CHECK: renamable $r4 = t2ADDrr killed renamable $r4, renamable $r4, 14 /* CC::al */, $noreg, $noreg
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit killed $d0
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renamable $s2 = VLDRS killed renamable $r0, 0, 14 /* CC::al */, $noreg
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renamable $d0 = VADDD killed renamable $d0, renamable $d0, 14 /* CC::al */, $noreg
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VSTRS killed renamable $s2, killed renamable $r1, 0, 14 /* CC::al */, $noreg
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renamable $r3 = t2ADDrr killed renamable $r3, renamable $r3, 14 /* CC::al */, $noreg, $noreg
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t2STRi12 killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg
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renamable $r4 = t2ADDrr killed renamable $r4, renamable $r4, 14 /* CC::al */, $noreg, $noreg
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tBX_RET 14 /* CC::al */, $noreg, implicit $d0
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...
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@ -253,23 +253,23 @@ vstr.f32 s0, [r0]
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# CHECK-NEXT: [0.0] - M7UnitALU
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# CHECK-NEXT: [0.1] - M7UnitALU
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# CHECK-NEXT: [1] - M7UnitBranch
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# CHECK-NEXT: [2.0] - M7UnitLoad
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# CHECK-NEXT: [2.1] - M7UnitLoad
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# CHECK-NEXT: [3] - M7UnitMAC
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# CHECK-NEXT: [4] - M7UnitSIMD
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# CHECK-NEXT: [5] - M7UnitShift1
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# CHECK-NEXT: [6] - M7UnitShift2
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# CHECK-NEXT: [7] - M7UnitStore
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# CHECK-NEXT: [8] - M7UnitVFP
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# CHECK-NEXT: [9.0] - M7UnitVPort
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# CHECK-NEXT: [9.1] - M7UnitVPort
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# CHECK-NEXT: [2] - M7UnitLoadH
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# CHECK-NEXT: [3] - M7UnitLoadL
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# CHECK-NEXT: [4] - M7UnitMAC
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# CHECK-NEXT: [5] - M7UnitSIMD
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# CHECK-NEXT: [6] - M7UnitShift1
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# CHECK-NEXT: [7] - M7UnitShift2
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# CHECK-NEXT: [8] - M7UnitStore
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# CHECK-NEXT: [9] - M7UnitVFP
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# CHECK-NEXT: [10] - M7UnitVPortH
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# CHECK-NEXT: [11] - M7UnitVPortL
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0.0] [0.1] [1] [2.0] [2.1] [3] [4] [5] [6] [7] [8] [9.0] [9.1]
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# CHECK-NEXT: - - - 1.00 1.00 - - - - 2.00 104.00 81.00 81.00
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# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
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# CHECK-NEXT: - - - 1.50 1.50 - - - - 2.00 104.00 81.00 81.00
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0.0] [0.1] [1] [2.0] [2.1] [3] [4] [5] [6] [7] [8] [9.0] [9.1] Instructions:
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# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] Instructions:
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# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vabs.f32 s0, s2
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# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vabs.f64 d0, d2
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# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vadd.f32 s0, s2, s1
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@ -384,7 +384,7 @@ vstr.f32 s0, [r0]
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# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vsqrt.f64 d0, d2
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# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vsub.f32 s0, s2, s1
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# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vsub.f64 d0, d2, d1
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# CHECK-NEXT: - - - 0.50 0.50 - - - - - - 1.00 1.00 vldr d0, [r0]
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# CHECK-NEXT: - - - 1.00 1.00 - - - - - - 1.00 1.00 vldr d0, [r0]
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# CHECK-NEXT: - - - 0.50 0.50 - - - - - - 0.50 0.50 vldr s0, [r0]
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# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 1.00 vstr d0, [r0]
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# CHECK-NEXT: - - - - - - - - - 1.00 - 0.50 0.50 vstr s0, [r0]
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@ -862,23 +862,23 @@ yield
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# CHECK-NEXT: [0.0] - M7UnitALU
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# CHECK-NEXT: [0.1] - M7UnitALU
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# CHECK-NEXT: [1] - M7UnitBranch
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# CHECK-NEXT: [2.0] - M7UnitLoad
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# CHECK-NEXT: [2.1] - M7UnitLoad
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# CHECK-NEXT: [3] - M7UnitMAC
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# CHECK-NEXT: [4] - M7UnitSIMD
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# CHECK-NEXT: [5] - M7UnitShift1
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# CHECK-NEXT: [6] - M7UnitShift2
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# CHECK-NEXT: [7] - M7UnitStore
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# CHECK-NEXT: [8] - M7UnitVFP
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# CHECK-NEXT: [9.0] - M7UnitVPort
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# CHECK-NEXT: [9.1] - M7UnitVPort
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# CHECK-NEXT: [2] - M7UnitLoadH
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# CHECK-NEXT: [3] - M7UnitLoadL
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# CHECK-NEXT: [4] - M7UnitMAC
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# CHECK-NEXT: [5] - M7UnitSIMD
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# CHECK-NEXT: [6] - M7UnitShift1
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# CHECK-NEXT: [7] - M7UnitShift2
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# CHECK-NEXT: [8] - M7UnitStore
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# CHECK-NEXT: [9] - M7UnitVFP
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# CHECK-NEXT: [10] - M7UnitVPortH
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# CHECK-NEXT: [11] - M7UnitVPortL
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0.0] [0.1] [1] [2.0] [2.1] [3] [4] [5] [6] [7] [8] [9.0] [9.1]
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# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
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# CHECK-NEXT: 125.00 125.00 - 35.00 35.00 43.00 90.00 88.00 2.00 45.00 - - -
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0.0] [0.1] [1] [2.0] [2.1] [3] [4] [5] [6] [7] [8] [9.0] [9.1] Instructions:
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# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] Instructions:
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# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - adc r0, r1, #0
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# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - adcs r0, r1, #0
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# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - adcs r0, r1
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@ -34,26 +34,26 @@ vldr d0, [r1]
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# CHECK-NEXT: [0.0] - M7UnitALU
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# CHECK-NEXT: [0.1] - M7UnitALU
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# CHECK-NEXT: [1] - M7UnitBranch
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# CHECK-NEXT: [2.0] - M7UnitLoad
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# CHECK-NEXT: [2.1] - M7UnitLoad
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# CHECK-NEXT: [3] - M7UnitMAC
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# CHECK-NEXT: [4] - M7UnitSIMD
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# CHECK-NEXT: [5] - M7UnitShift1
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# CHECK-NEXT: [6] - M7UnitShift2
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# CHECK-NEXT: [7] - M7UnitStore
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# CHECK-NEXT: [8] - M7UnitVFP
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# CHECK-NEXT: [9.0] - M7UnitVPort
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# CHECK-NEXT: [9.1] - M7UnitVPort
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# CHECK-NEXT: [2] - M7UnitLoadH
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# CHECK-NEXT: [3] - M7UnitLoadL
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# CHECK-NEXT: [4] - M7UnitMAC
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# CHECK-NEXT: [5] - M7UnitSIMD
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# CHECK-NEXT: [6] - M7UnitShift1
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# CHECK-NEXT: [7] - M7UnitShift2
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# CHECK-NEXT: [8] - M7UnitStore
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# CHECK-NEXT: [9] - M7UnitVFP
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# CHECK-NEXT: [10] - M7UnitVPortH
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# CHECK-NEXT: [11] - M7UnitVPortL
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0.0] [0.1] [1] [2.0] [2.1] [3] [4] [5] [6] [7] [8] [9.0] [9.1]
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# CHECK-NEXT: 1.00 1.00 - - 1.00 - - - - - - - 2.00
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# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
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# CHECK-NEXT: 1.00 1.00 - 1.00 1.00 - - - - - - 1.00 1.00
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0.0] [0.1] [1] [2.0] [2.1] [3] [4] [5] [6] [7] [8] [9.0] [9.1] Instructions:
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# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] Instructions:
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# CHECK-NEXT: - 1.00 - - - - - - - - - - - add.w r1, r1, #1
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# CHECK-NEXT: 1.00 - - - - - - - - - - - - add.w r1, r1, #2
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# CHECK-NEXT: - - - - 1.00 - - - - - - - 2.00 vldr d0, [r1]
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# CHECK-NEXT: - - - 1.00 1.00 - - - - - - 1.00 1.00 vldr d0, [r1]
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# CHECK: Timeline view:
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# CHECK-NEXT: Index 012345
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