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[mips] Guard indirect and tailcall pseudo instructions correctly. 

Previously these pseudo instructions were not guarded by ISA, so their
select was dependant on the ordering of the entries in the DAG matcher.

Reviewers: atanasyan

Differential Revision: https://reviews.llvm.org/D39723

llvm-svn: 317681
This commit is contained in:
Simon Dardis 2017-11-08 11:13:44 +00:00
parent 17921d9e21
commit 789f7ca265
5 changed files with 97 additions and 12 deletions
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7
llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td
View File

@ -1883,3 +1883,10 @@ let AddedComplexity = 41 in {
}
def TAILCALL_MMR6 : TailCall<BC_MMR6, brtarget26_mm>, ISA_MICROMIPS32R6;
def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
(TAILCALL_MMR6 tglobaladdr:$dst)>, ISA_MICROMIPS32R6;
def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
(TAILCALL_MMR6 texternalsym:$dst)>, ISA_MICROMIPS32R6;

6
llvm/lib/Target/Mips/MicroMipsInstrInfo.td
View File

@ -1062,12 +1062,12 @@ let Predicates = [InMicroMips] in {
(LW_MM addr:$addr)>;
def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
(SUBu_MM GPR32:$lhs, GPR32:$rhs)>;
}
def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
(TAILCALL_MM tglobaladdr:$dst)>, ISA_MIPS1_NOT_32R6_64R6;
(TAILCALL_MM tglobaladdr:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6;
def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
(TAILCALL_MM texternalsym:$dst)>, ISA_MIPS1_NOT_32R6_64R6;
}
(TAILCALL_MM texternalsym:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6;
let AddedComplexity = 40 in {
def : MipsPat<(i32 (sextloadi16 addrRegImm:$a)),

9
llvm/lib/Target/Mips/MipsInstrInfo.td
View File

@ -212,6 +212,8 @@ def HasMicroMips64r6 : Predicate<"Subtarget->inMicroMips64r6Mode()">,
AssemblerPredicate<"FeatureMicroMips,FeatureMips64r6">;
def InMips16Mode : Predicate<"Subtarget->inMips16Mode()">,
AssemblerPredicate<"FeatureMips16">;
def NotInMips16Mode : Predicate<"!Subtarget->inMips16Mode()">,
AssemblerPredicate<"!FeatureMips16">;
def HasCnMips : Predicate<"Subtarget->hasCnMips()">,
AssemblerPredicate<"FeatureCnMips">;
def NotCnMips : Predicate<"!Subtarget->hasCnMips()">,
@ -1544,7 +1546,7 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
PseudoInstExpansion<(JumpInst Opnd:$target)>;
class TailCallReg<RegisterOperand RO> :
MipsPseudo<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>;
PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>;
}
class BAL_BR_Pseudo<Instruction RealInst> :
@ -2087,7 +2089,7 @@ def BLTZALL : MMRel, BGEZAL_FT<"bltzall", brtarget, GPR32Opnd>,
BGEZAL_FM<0x12>, ISA_MIPS2_NOT_32R6_64R6;
def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
let Predicates = [NotInMicroMips] in {
let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips] in {
def TAILCALL : TailCall<J, jmptarget>;
}
@ -2104,6 +2106,7 @@ class PseudoIndirectBranchBase<RegisterOperand RO> :
let isBranch = 1;
let isIndirectBranch = 1;
bit isCTI = 1;
let Predicates = [NotInMips16Mode];
}
def PseudoIndirectBranch : PseudoIndirectBranchBase<GPR32Opnd>;
@ -2777,10 +2780,12 @@ def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
// (JALR GPR32:$dst)>;
// Tail call
let AdditionalPredicates = [NotInMicroMips] in {
def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
(TAILCALL tglobaladdr:$dst)>;
def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
(TAILCALL texternalsym:$dst)>;
}
// hi/lo relocs
multiclass MipsHiLoRelocs<Instruction Lui, Instruction Addiu,
Register ZeroReg, RegisterOperand GPROpnd> {

60
llvm/test/CodeGen/Mips/brind-tailcall.ll Normal file
View File

@ -0,0 +1,60 @@
; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1 \
; RUN: -relocation-model=pic < %s 2>&1 | FileCheck --check-prefix=PIC %s
; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1 \
; RUN: -relocation-model=static < %s 2>&1 | FileCheck --check-prefix=STATIC %s
; RUN: llc -march=mips64 -debug-only=isel -mips-tail-calls=1 \
; RUN: -relocation-model=pic < %s 2>&1 | FileCheck --check-prefix=PIC64 %s
; RUN: llc -march=mips64 -debug-only=isel -mips-tail-calls=1 \
; RUN: -relocation-model=static < %s 2>&1 | FileCheck --check-prefix=STATIC64 %s
; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1 \
; RUN: -relocation-model=pic -mattr=+micromips < %s 2>&1 | FileCheck --check-prefix=PIC %s
; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1 \
; RUN: -relocation-model=static -mattr=+micromips < %s 2>&1 | FileCheck --check-prefix=STATIC-MM %s
; RUN: llc -march=mips -mcpu=mips32r6 -debug-only=isel -mips-tail-calls=1 \
; RUN: -relocation-model=pic -mattr=+micromips < %s 2>&1 | FileCheck --check-prefix=PIC %s
; RUN: llc -march=mips -mcpu=mips32r6 -debug-only=isel -mips-tail-calls=1 \
; RUN: -relocation-model=static -mattr=+micromips < %s 2>&1 | FileCheck --check-prefix=STATIC-MM %s
; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1 \
; RUN: -relocation-model=pic -mattr=+mips16 < %s 2>&1 | FileCheck --check-prefix=MIPS16 %s
; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1 \
; RUN: -relocation-model=static -mattr=+mips16 < %s 2>&1 | FileCheck --check-prefix=MIPS16 %s
; REQUIRES: asserts
; Test that the correct pseudo instructions are generated for indirect
; branches and tail calls. Previously, the order of the DAG matcher table
; determined if the correct instruction was selected for mips16.
declare protected void @a()
define void @test1(i32 %a) {
entry:
%0 = trunc i32 %a to i1
%1 = select i1 %0,
i8* blockaddress(@test1, %bb),
i8* blockaddress(@test1, %bb6)
indirectbr i8* %1, [label %bb, label %bb6]
; STATIC: PseudoIndirectBranch
; STATIC-MM: PseudoIndirectBranch
; STATIC-NOT: PseudoIndirectBranch64
; STATIC64: PseudoIndirectBranch64
; PIC: PseudoIndirectBranch
; PIC-NOT: PseudoIndirectBranch64
; PIC64: PseudoIndirectBranch64
; MIPS16: JrcRx16
bb:
ret void
bb6:
tail call void @a()
; STATIC: TAILCALL
; STATIC-NOT: TAILCALL_MM
; STATIC-MM: TAILCALL_MM
; PIC: TAILCALLREG
; PIC-NOT: TAILCALLREG64
; PIC64: TAILCALLREG64
; MIPS16: RetRA16
ret void
}

15
llvm/test/CodeGen/Mips/tailcall/tailcall.ll
View File

@ -27,7 +27,7 @@
; RUN: llc -march=mipsel -relocation-model=pic -mcpu=mips32r6 -mattr=+micromips \
; RUN: -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,PIC32MM
; RUN: llc -march=mipsel -relocation-model=static -mcpu=mips32r6 \
; RUN: -mattr=+micromips -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,STATIC32
; RUN: -mattr=+micromips -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,STATIC32MMR6
; RUN: llc -march=mips64el -relocation-model=pic -mcpu=mips64r6 \
; RUN: -mattr=+micromips -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=PIC64R6MM
; RUN: llc -march=mips64el -relocation-model=static -mcpu=mips64r6 \
@ -51,6 +51,7 @@ entry:
; PIC32MM: jalr $25
; PIC32R6: jalr $25
; STATIC32: jal
; STATIC32MMR6: jal
; N64: jalr $25
; N64R6: jalr $25
; PIC16: jalrc
@ -68,6 +69,7 @@ entry:
; PIC32MM: jalr $25
; PIC32R6: jalr $25
; STATIC32: jal
; STATIC32MMR6: jal
; N64: jalr $25
; N64R6: jalr $25
; PIC16: jalrc
@ -85,6 +87,7 @@ entry:
; PIC32R6: jalr $25
; PIC32MM: jalr $25
; STATIC32: jal
; STATIC32MMR6: jal
; N64: jalr $25
; N64R6: jalr $25
; PIC16: jalrc
@ -102,6 +105,7 @@ entry:
; PIC32R6: jalr $25
; PIC32MM: jalr $25
; STATIC32: jal
; SATATIC32MMR6: jal
; PIC64: jalr $25
; STATIC64: jal
; N64R6: jalr $25
@ -120,6 +124,7 @@ entry:
; PIC32R6: jr $25
; PIC32MM: jr
; STATIC32: j
; STATIC32MMR6: bc
; PIC64: jr $25
; STATIC64: j
; PIC16: jalrc
@ -161,6 +166,7 @@ entry:
; PIC32R6: jrc $25
; PIC32MM: jrc
; STATIC32: j
; STATIC32MMR6: bc
; PIC64: jr $25
; PIC64R6: jrc $25
; PIC64R6MM: jr $25
@ -178,6 +184,7 @@ entry:
; PIC32R6: jalr $25
; PIC32MM: jalr $25
; STATIC32: jal
; STATIC32MMR6: jal
; PIC64: jalr $25
; STATIC64: jal
; PIC16: jalrc
@ -199,6 +206,7 @@ entry:
; PIC32R6: jrc $25
; PIC32MM: jrc
; STATIC32: j
; STATIC32MMR6: bc
; PIC64: jr $25
; STATIC64: j
; PIC64R6: jrc $25
@ -214,6 +222,7 @@ entry:
; PIC32R6: jalrc $25
; PIC32MM: jalr $25
; STATIC32: jal
; STATIC32MMR6: jal
; STATIC64: jal
; PIC64: jalr $25
; PIC64R6: jalrc $25
@ -232,6 +241,7 @@ entry:
; PIC32R6: jalr $25
; PIC32MM: jalr $25
; STATIC32: jal
; STATIC32MMR6: jal
; STATIC64: jal
; PIC64: jalr $25
; PIC64R6: jalr $25
@ -250,6 +260,7 @@ entry:
; PIC32R6: jalrc $25
; PIC32MM: jalr $25
; STATIC32: jal
; STATIC32MMR6: jal
; STATIC64: jal
; PIC64: jalr $25
; PIC64R6: jalrc $25
@ -270,6 +281,7 @@ entry:
; PIC32R6: jalrc $25
; PIC32MM: jalr $25
; STATIC32: jal
; STATIC32MMR6: jal
; STATIC64: jal
; PIC64: jalr $25
; PIC64R6: jalrc $25
@ -290,6 +302,7 @@ entry:
; PIC32R6: jalr $25
; PIC32MM: jalr $25
; STATIC32: jal
; STATIC32MMR6: jal
; STATIC64: jal
; PIC64R6: jalr $25
; PIC64: jalr $25