forked from OSchip/llvm-project
[mips] Guard indirect and tailcall pseudo instructions correctly.
Previously these pseudo instructions were not guarded by ISA, so their select was dependant on the ordering of the entries in the DAG matcher. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D39723 llvm-svn: 317681
This commit is contained in:
Simon Dardis
parent
17921d9e21
commit
789f7ca265
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@ -1883,3 +1883,10 @@ let AddedComplexity = 41 in {
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}
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def TAILCALL_MMR6 : TailCall<BC_MMR6, brtarget26_mm>, ISA_MICROMIPS32R6;
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def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
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(TAILCALL_MMR6 tglobaladdr:$dst)>, ISA_MICROMIPS32R6;
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def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
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(TAILCALL_MMR6 texternalsym:$dst)>, ISA_MICROMIPS32R6;
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@ -1062,13 +1062,13 @@ let Predicates = [InMicroMips] in {
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(LW_MM addr:$addr)>;
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def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
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(SUBu_MM GPR32:$lhs, GPR32:$rhs)>;
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def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
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(TAILCALL_MM tglobaladdr:$dst)>, ISA_MIPS1_NOT_32R6_64R6;
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def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
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(TAILCALL_MM texternalsym:$dst)>, ISA_MIPS1_NOT_32R6_64R6;
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}
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def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
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(TAILCALL_MM tglobaladdr:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6;
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def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
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(TAILCALL_MM texternalsym:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6;
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let AddedComplexity = 40 in {
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def : MipsPat<(i32 (sextloadi16 addrRegImm:$a)),
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(LH_MM addrRegImm:$a)>;
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@ -212,6 +212,8 @@ def HasMicroMips64r6 : Predicate<"Subtarget->inMicroMips64r6Mode()">,
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AssemblerPredicate<"FeatureMicroMips,FeatureMips64r6">;
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def InMips16Mode : Predicate<"Subtarget->inMips16Mode()">,
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AssemblerPredicate<"FeatureMips16">;
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def NotInMips16Mode : Predicate<"!Subtarget->inMips16Mode()">,
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AssemblerPredicate<"!FeatureMips16">;
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def HasCnMips : Predicate<"Subtarget->hasCnMips()">,
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AssemblerPredicate<"FeatureCnMips">;
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def NotCnMips : Predicate<"!Subtarget->hasCnMips()">,
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@ -1544,7 +1546,7 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
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PseudoInstExpansion<(JumpInst Opnd:$target)>;
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class TailCallReg<RegisterOperand RO> :
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MipsPseudo<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>;
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PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>;
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}
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class BAL_BR_Pseudo<Instruction RealInst> :
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@ -2087,7 +2089,7 @@ def BLTZALL : MMRel, BGEZAL_FT<"bltzall", brtarget, GPR32Opnd>,
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BGEZAL_FM<0x12>, ISA_MIPS2_NOT_32R6_64R6;
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def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
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let Predicates = [NotInMicroMips] in {
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let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips] in {
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def TAILCALL : TailCall<J, jmptarget>;
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}
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@ -2104,6 +2106,7 @@ class PseudoIndirectBranchBase<RegisterOperand RO> :
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let isBranch = 1;
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let isIndirectBranch = 1;
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bit isCTI = 1;
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let Predicates = [NotInMips16Mode];
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}
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def PseudoIndirectBranch : PseudoIndirectBranchBase<GPR32Opnd>;
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@ -2777,10 +2780,12 @@ def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
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// (JALR GPR32:$dst)>;
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// Tail call
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def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
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(TAILCALL tglobaladdr:$dst)>;
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def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
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(TAILCALL texternalsym:$dst)>;
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let AdditionalPredicates = [NotInMicroMips] in {
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def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
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(TAILCALL tglobaladdr:$dst)>;
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def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
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(TAILCALL texternalsym:$dst)>;
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}
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// hi/lo relocs
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multiclass MipsHiLoRelocs<Instruction Lui, Instruction Addiu,
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Register ZeroReg, RegisterOperand GPROpnd> {
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@ -0,0 +1,60 @@
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; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1 \
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; RUN: -relocation-model=pic < %s 2>&1 | FileCheck --check-prefix=PIC %s
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; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1 \
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; RUN: -relocation-model=static < %s 2>&1 | FileCheck --check-prefix=STATIC %s
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; RUN: llc -march=mips64 -debug-only=isel -mips-tail-calls=1 \
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; RUN: -relocation-model=pic < %s 2>&1 | FileCheck --check-prefix=PIC64 %s
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; RUN: llc -march=mips64 -debug-only=isel -mips-tail-calls=1 \
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; RUN: -relocation-model=static < %s 2>&1 | FileCheck --check-prefix=STATIC64 %s
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; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1 \
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; RUN: -relocation-model=pic -mattr=+micromips < %s 2>&1 | FileCheck --check-prefix=PIC %s
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; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1 \
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; RUN: -relocation-model=static -mattr=+micromips < %s 2>&1 | FileCheck --check-prefix=STATIC-MM %s
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; RUN: llc -march=mips -mcpu=mips32r6 -debug-only=isel -mips-tail-calls=1 \
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; RUN: -relocation-model=pic -mattr=+micromips < %s 2>&1 | FileCheck --check-prefix=PIC %s
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; RUN: llc -march=mips -mcpu=mips32r6 -debug-only=isel -mips-tail-calls=1 \
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; RUN: -relocation-model=static -mattr=+micromips < %s 2>&1 | FileCheck --check-prefix=STATIC-MM %s
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; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1 \
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; RUN: -relocation-model=pic -mattr=+mips16 < %s 2>&1 | FileCheck --check-prefix=MIPS16 %s
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; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1 \
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; RUN: -relocation-model=static -mattr=+mips16 < %s 2>&1 | FileCheck --check-prefix=MIPS16 %s
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; REQUIRES: asserts
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; Test that the correct pseudo instructions are generated for indirect
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; branches and tail calls. Previously, the order of the DAG matcher table
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; determined if the correct instruction was selected for mips16.
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declare protected void @a()
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define void @test1(i32 %a) {
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entry:
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%0 = trunc i32 %a to i1
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%1 = select i1 %0,
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i8* blockaddress(@test1, %bb),
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i8* blockaddress(@test1, %bb6)
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indirectbr i8* %1, [label %bb, label %bb6]
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; STATIC: PseudoIndirectBranch
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; STATIC-MM: PseudoIndirectBranch
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; STATIC-NOT: PseudoIndirectBranch64
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; STATIC64: PseudoIndirectBranch64
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; PIC: PseudoIndirectBranch
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; PIC-NOT: PseudoIndirectBranch64
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; PIC64: PseudoIndirectBranch64
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; MIPS16: JrcRx16
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bb:
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ret void
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bb6:
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tail call void @a()
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; STATIC: TAILCALL
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; STATIC-NOT: TAILCALL_MM
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; STATIC-MM: TAILCALL_MM
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; PIC: TAILCALLREG
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; PIC-NOT: TAILCALLREG64
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; PIC64: TAILCALLREG64
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; MIPS16: RetRA16
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ret void
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}
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@ -27,7 +27,7 @@
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; RUN: llc -march=mipsel -relocation-model=pic -mcpu=mips32r6 -mattr=+micromips \
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; RUN: -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,PIC32MM
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; RUN: llc -march=mipsel -relocation-model=static -mcpu=mips32r6 \
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; RUN: -mattr=+micromips -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,STATIC32
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; RUN: -mattr=+micromips -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,STATIC32MMR6
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; RUN: llc -march=mips64el -relocation-model=pic -mcpu=mips64r6 \
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; RUN: -mattr=+micromips -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=PIC64R6MM
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; RUN: llc -march=mips64el -relocation-model=static -mcpu=mips64r6 \
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@ -51,6 +51,7 @@ entry:
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; PIC32MM: jalr $25
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; PIC32R6: jalr $25
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; STATIC32: jal
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; STATIC32MMR6: jal
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; N64: jalr $25
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; N64R6: jalr $25
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; PIC16: jalrc
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@ -68,6 +69,7 @@ entry:
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; PIC32MM: jalr $25
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; PIC32R6: jalr $25
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; STATIC32: jal
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; STATIC32MMR6: jal
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; N64: jalr $25
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; N64R6: jalr $25
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; PIC16: jalrc
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@ -85,6 +87,7 @@ entry:
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; PIC32R6: jalr $25
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; PIC32MM: jalr $25
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; STATIC32: jal
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; STATIC32MMR6: jal
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; N64: jalr $25
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; N64R6: jalr $25
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; PIC16: jalrc
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@ -102,6 +105,7 @@ entry:
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; PIC32R6: jalr $25
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; PIC32MM: jalr $25
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; STATIC32: jal
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; SATATIC32MMR6: jal
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; PIC64: jalr $25
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; STATIC64: jal
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; N64R6: jalr $25
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@ -120,6 +124,7 @@ entry:
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; PIC32R6: jr $25
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; PIC32MM: jr
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; STATIC32: j
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; STATIC32MMR6: bc
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; PIC64: jr $25
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; STATIC64: j
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; PIC16: jalrc
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@ -161,6 +166,7 @@ entry:
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; PIC32R6: jrc $25
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; PIC32MM: jrc
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; STATIC32: j
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; STATIC32MMR6: bc
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; PIC64: jr $25
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; PIC64R6: jrc $25
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; PIC64R6MM: jr $25
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@ -178,6 +184,7 @@ entry:
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; PIC32R6: jalr $25
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; PIC32MM: jalr $25
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; STATIC32: jal
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; STATIC32MMR6: jal
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; PIC64: jalr $25
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; STATIC64: jal
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; PIC16: jalrc
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@ -199,6 +206,7 @@ entry:
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; PIC32R6: jrc $25
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; PIC32MM: jrc
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; STATIC32: j
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; STATIC32MMR6: bc
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; PIC64: jr $25
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; STATIC64: j
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; PIC64R6: jrc $25
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@ -214,6 +222,7 @@ entry:
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; PIC32R6: jalrc $25
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; PIC32MM: jalr $25
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; STATIC32: jal
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; STATIC32MMR6: jal
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; STATIC64: jal
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; PIC64: jalr $25
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; PIC64R6: jalrc $25
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@ -232,6 +241,7 @@ entry:
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; PIC32R6: jalr $25
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; PIC32MM: jalr $25
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; STATIC32: jal
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; STATIC32MMR6: jal
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; STATIC64: jal
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; PIC64: jalr $25
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; PIC64R6: jalr $25
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@ -250,6 +260,7 @@ entry:
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; PIC32R6: jalrc $25
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; PIC32MM: jalr $25
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; STATIC32: jal
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; STATIC32MMR6: jal
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; STATIC64: jal
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; PIC64: jalr $25
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; PIC64R6: jalrc $25
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@ -270,6 +281,7 @@ entry:
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; PIC32R6: jalrc $25
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; PIC32MM: jalr $25
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; STATIC32: jal
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; STATIC32MMR6: jal
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; STATIC64: jal
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; PIC64: jalr $25
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; PIC64R6: jalrc $25
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@ -290,6 +302,7 @@ entry:
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; PIC32R6: jalr $25
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; PIC32MM: jalr $25
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; STATIC32: jal
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; STATIC32MMR6: jal
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; STATIC64: jal
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; PIC64R6: jalr $25
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; PIC64: jalr $25
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