forked from OSchip/llvm-project
Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027.
llvm-svn: 141007
This commit is contained in:
Craig Topper
parent
e359bc09bb
commit
786bdb9e14
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@ -96,6 +96,10 @@ def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
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"Allow unaligned memory operands on vector/SIMD instructions">;
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def FeatureAES : SubtargetFeature<"aes", "HasAES", "true",
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"Enable AES instructions">;
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def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true",
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"Support MOVBE instruction">;
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def FeatureRDRAND : SubtargetFeature<"rdrand", "HasRDRAND", "true",
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"Support RDRAND instruction">;
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//===----------------------------------------------------------------------===//
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// X86 processors supported.
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@ -473,6 +473,8 @@ def HasAES : Predicate<"Subtarget->hasAES()">;
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def HasCLMUL : Predicate<"Subtarget->hasCLMUL()">;
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def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
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def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
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def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
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def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
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def FPStackf32 : Predicate<"!Subtarget->hasXMM()">;
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def FPStackf64 : Predicate<"!Subtarget->hasXMMInt()">;
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def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
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@ -1296,6 +1298,36 @@ def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$src), (ins GR16:$dst),
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def ARPL16mr : I<0x63, MRMSrcMem, (outs GR16:$src), (ins i16mem:$dst),
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"arpl\t{$src, $dst|$dst, $src}", []>, Requires<[In32BitMode]>;
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//===----------------------------------------------------------------------===//
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// MOVBE Instructions
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//
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let Predicates = [HasMOVBE] in {
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def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
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"movbe{w}\t{$src, $dst|$dst, $src}", []>, OpSize, T8;
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def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
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"movbe{l}\t{$src, $dst|$dst, $src}", []>, T8;
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def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
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"movbe{q}\t{$src, $dst|$dst, $src}", []>, T8;
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def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
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"movbe{w}\t{$src, $dst|$dst, $src}", []>, OpSize, T8;
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def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
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"movbe{l}\t{$src, $dst|$dst, $src}", []>, T8;
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def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
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"movbe{q}\t{$src, $dst|$dst, $src}", []>, T8;
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}
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//===----------------------------------------------------------------------===//
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// RDRAND Instruction
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//
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let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
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def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
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"rdrand{w}\t$dst", []>, OpSize, TB;
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def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
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"rdrand{l}\t$dst", []>, TB;
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def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
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"rdrand{q}\t$dst", []>, TB;
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}
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//===----------------------------------------------------------------------===//
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// Subsystems.
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//===----------------------------------------------------------------------===//
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@ -6748,4 +6748,3 @@ let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
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def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
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[(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
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}
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@ -203,8 +203,10 @@ void X86Subtarget::AutoDetectSubtargetFeatures() {
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HasCLMUL = IsIntel && ((ECX >> 1) & 0x1); ToggleFeature(X86::FeatureCLMUL);
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HasFMA3 = IsIntel && ((ECX >> 12) & 0x1); ToggleFeature(X86::FeatureFMA3);
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HasMOVBE = IsIntel && ((ECX >> 22) & 0x1); ToggleFeature(X86::FeatureMOVBE);
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HasPOPCNT = IsIntel && ((ECX >> 23) & 0x1); ToggleFeature(X86::FeaturePOPCNT);
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HasAES = IsIntel && ((ECX >> 25) & 0x1); ToggleFeature(X86::FeatureAES);
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HasRDRAND = IsIntel && ((ECX >> 30) & 0x1); ToggleFeature(X86::FeatureRDRAND);
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HasCmpxchg16b = ((ECX >> 13) & 0x1); ToggleFeature(X86::FeatureCMPXCHG16B);
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if (IsIntel || IsAMD) {
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@ -254,6 +256,8 @@ X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU,
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, HasCLMUL(false)
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, HasFMA3(false)
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, HasFMA4(false)
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, HasMOVBE(false)
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, HasRDRAND(false)
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, IsBTMemSlow(false)
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, IsUAMemFast(false)
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, HasVectorUAMem(false)
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@ -90,6 +90,12 @@ protected:
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/// HasFMA4 - Target has 4-operand fused multiply-add
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bool HasFMA4;
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/// HasMOVBE - True if the processor has the MOVBE instruction;
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bool HasMOVBE;
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/// HasRDRAND - True if the processor has the RDRAND instruction;
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bool HasRDRAND;
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/// IsBTMemSlow - True if BT (bit test) of memory instructions are slow.
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bool IsBTMemSlow;
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@ -172,6 +178,8 @@ public:
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bool hasCLMUL() const { return HasCLMUL; }
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bool hasFMA3() const { return HasFMA3; }
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bool hasFMA4() const { return HasFMA4; }
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bool hasMOVBE() const { return HasMOVBE; }
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bool hasRDRAND() const { return HasRDRAND; }
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bool isBTMemSlow() const { return IsBTMemSlow; }
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bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
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bool hasVectorUAMem() const { return HasVectorUAMem; }
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@ -368,3 +368,30 @@
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# CHECK: vaddps %xmm3, %xmm15, %xmm0
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0xc4 0xe1 0x00 0x58 0xc3
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# CHECK: movbel (%rax), %eax
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0x0f 0x38 0xf0 0x00
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# CHECK: movbel %eax, (%rax)
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0x0f 0x38 0xf1 0x00
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# CHECK: movbew (%rax), %ax
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0x66 0x0f 0x38 0xf0 0x00
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# CHECK: movbew %ax, (%rax)
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0x66 0x0f 0x38 0xf1 0x00
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# CHECK: movbeq (%rax), %rax
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0x48 0x0f 0x38 0xf0 0x00
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# CHECK: movbeq %rax, (%rax)
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0x48 0x0f 0x38 0xf1 0x00
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# CHECK: rdrandw %ax
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0x66 0x0f 0xc7 0xf0
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# CHECK: rdrandl %eax
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0x0f 0xc7 0xf0
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# CHECK: rdrandq %rax
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0x48 0x0f 0xc7 0xf0
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@ -387,3 +387,21 @@
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# CHECK: vaddps %xmm3, %xmm7, %xmm0
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0xc4 0xe1 0x00 0x58 0xc3
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# CHECK: movbel (%eax), %eax
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0x0f 0x38 0xf0 0x00
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# CHECK: movbel %eax, (%eax)
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0x0f 0x38 0xf1 0x00
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# CHECK: movbew (%eax), %ax
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0x66 0x0f 0x38 0xf0 0x00
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# CHECK: movbew %ax, (%eax)
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0x66 0x0f 0x38 0xf1 0x00
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# CHECK: rdrandw %ax
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0x66 0x0f 0xc7 0xf0
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# CHECK: rdrandl %eax
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0x0f 0xc7 0xf0
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