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[mips] SYNC $stype instruction was added in Mips32 

but SYNC with an implied operand ($stype = 0) is valid since Mips2.

llvm-svn: 211185
This commit is contained in:
Matheus Almeida 2014-06-18 17:10:30 +00:00
parent 24d8b84838
commit 784f797d4c
18 changed files with 68 additions and 3 deletions
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8
llvm/lib/Target/Mips/MipsInstrInfo.td
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@ -1156,7 +1156,7 @@ def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>,
ISA_MIPS1_NOT_32R6_64R6; ISA_MIPS1_NOT_32R6_64R6;
} }
def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM; def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS32;
def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>; def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>; def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>; def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
@ -1488,6 +1488,8 @@ def : MipsInstAlias<"sra $rd, $rt, $rs",
(SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
def : MipsInstAlias<"srl $rd, $rt, $rs", def : MipsInstAlias<"srl $rd, $rt, $rs",
(SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
def : MipsInstAlias<"sync",
(SYNC 0), 1>, ISA_MIPS2;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Assembler Pseudo Instructions // Assembler Pseudo Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
@ -1540,6 +1542,10 @@ let AdditionalPredicates = [NotDSP] in {
(ADDiu GPR32:$src, imm:$imm)>; (ADDiu GPR32:$src, imm:$imm)>;
} }
// SYNC
def : MipsPat<(MipsSync (i32 immz)),
(SYNC 0)>, ISA_MIPS2;
// Call // Call
def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
(JAL tglobaladdr:$dst)>; (JAL tglobaladdr:$dst)>;

4
llvm/test/CodeGen/Mips/atomic.ll
View File

@ -344,11 +344,11 @@ entry:
; ALL-LABEL: CheckSync: ; ALL-LABEL: CheckSync:
; ALL: sync 0 ; ALL: sync
; ALL: ll ; ALL: ll
; ALL: sc ; ALL: sc
; ALL: beq ; ALL: beq
; ALL: sync 0 ; ALL: sync
} }
; make sure that this assertion in ; make sure that this assertion in

1
llvm/test/MC/Mips/mips1/invalid-mips2.s
View File

@ -21,3 +21,4 @@
tnei $t4,-29647 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled tnei $t4,-29647 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
trunc.w.d $f22,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled trunc.w.d $f22,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
trunc.w.s $f28,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled trunc.w.s $f28,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
sync # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

10
llvm/test/MC/Mips/mips1/invalid-mips32.s Normal file
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@ -0,0 +1,10 @@
# Instructions that are invalid
#
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 \
# RUN: 2>%t1
# RUN: FileCheck %s < %t1
.set noat
sync 0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

2
llvm/test/MC/Mips/mips2/invalid-mips32.s
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@ -40,3 +40,5 @@
msubu $15,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled msubu $15,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
mtc0 $9,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mtc0 $9,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
mul $s0,$s4,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mul $s0,$s4,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
sync 0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

1
llvm/test/MC/Mips/mips2/valid.s
View File

@ -122,6 +122,7 @@
swc3 $10,-32265($k0) swc3 $10,-32265($k0)
swl $15,13694($s3) swl $15,13694($s3)
swr $s1,-26590($14) swr $s1,-26590($14)
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
teqi $s5,-17504 teqi $s5,-17504
tgei $s1,5025 tgei $s1,5025
tgeiu $sp,-28621 tgeiu $sp,-28621

10
llvm/test/MC/Mips/mips3/invalid-mips32.s Normal file
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@ -0,0 +1,10 @@
# Instructions that are invalid
#
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips3 \
# RUN: 2>%t1
# RUN: FileCheck %s < %t1
.set noat
sync 0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

1
llvm/test/MC/Mips/mips3/valid.s
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@ -179,6 +179,7 @@
swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30] swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30]
swl $15,13694($s3) swl $15,13694($s3)
swr $s1,-26590($14) swr $s1,-26590($14)
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
teqi $s5,-17504 teqi $s5,-17504
tgei $s1,5025 tgei $s1,5025
tgeiu $sp,-28621 tgeiu $sp,-28621

2
llvm/test/MC/Mips/mips32/valid.s
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@ -147,6 +147,8 @@
swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30] swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30]
swl $15,13694($s3) swl $15,13694($s3)
swr $s1,-26590($14) swr $s1,-26590($14)
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
teqi $s5,-17504 teqi $s5,-17504
tgei $s1,5025 tgei $s1,5025
tgeiu $sp,-28621 tgeiu $sp,-28621

2
llvm/test/MC/Mips/mips32r2/valid.s
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@ -177,6 +177,8 @@
swl $15,13694($s3) swl $15,13694($s3)
swr $s1,-26590($14) swr $s1,-26590($14)
swxc1 $f19,$12($k0) swxc1 $f19,$12($k0)
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
teqi $s5,-17504 teqi $s5,-17504
tgei $s1,5025 tgei $s1,5025
tgeiu $sp,-28621 tgeiu $sp,-28621

2
llvm/test/MC/Mips/mips32r6/valid.s
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@ -147,3 +147,5 @@
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50] clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50]
ssnop # WARNING: [[@LINE]]:9: warning: ssnop is deprecated for MIPS32r6 and is equivalent to a nop instruction ssnop # WARNING: [[@LINE]]:9: warning: ssnop is deprecated for MIPS32r6 and is equivalent to a nop instruction
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]

10
llvm/test/MC/Mips/mips4/invalid-mips32.s Normal file
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@ -0,0 +1,10 @@
# Instructions that are invalid
#
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips4 \
# RUN: 2>%t1
# RUN: FileCheck %s < %t1
.set noat
sync 0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

1
llvm/test/MC/Mips/mips4/valid.s
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@ -198,6 +198,7 @@
swl $15,13694($s3) swl $15,13694($s3)
swr $s1,-26590($14) swr $s1,-26590($14)
swxc1 $f19,$12($k0) swxc1 $f19,$12($k0)
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
teqi $s5,-17504 teqi $s5,-17504
tgei $s1,5025 tgei $s1,5025
tgeiu $sp,-28621 tgeiu $sp,-28621

10
llvm/test/MC/Mips/mips5/invalid-mips32.s Normal file
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@ -0,0 +1,10 @@
# Instructions that are invalid
#
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips5 \
# RUN: 2>%t1
# RUN: FileCheck %s < %t1
.set noat
sync 0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

1
llvm/test/MC/Mips/mips5/valid.s
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@ -200,6 +200,7 @@
swl $15,13694($s3) swl $15,13694($s3)
swr $s1,-26590($14) swr $s1,-26590($14)
swxc1 $f19,$12($k0) swxc1 $f19,$12($k0)
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
teqi $s5,-17504 teqi $s5,-17504
tgei $s1,5025 tgei $s1,5025
tgeiu $sp,-28621 tgeiu $sp,-28621

2
llvm/test/MC/Mips/mips64/valid.s
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@ -214,6 +214,8 @@
swl $15,13694($s3) swl $15,13694($s3)
swr $s1,-26590($14) swr $s1,-26590($14)
swxc1 $f19,$12($k0) swxc1 $f19,$12($k0)
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
teqi $s5,-17504 teqi $s5,-17504
tgei $s1,5025 tgei $s1,5025
tgeiu $sp,-28621 tgeiu $sp,-28621

2
llvm/test/MC/Mips/mips64r2/valid.s
View File

@ -241,6 +241,8 @@
swl $15,13694($s3) swl $15,13694($s3)
swr $s1,-26590($14) swr $s1,-26590($14)
swxc1 $f19,$12($k0) swxc1 $f19,$12($k0)
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
teqi $s5,-17504 teqi $s5,-17504
tgei $s1,5025 tgei $s1,5025
tgeiu $sp,-28621 tgeiu $sp,-28621

2
llvm/test/MC/Mips/mips64r6/valid.s
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@ -165,3 +165,5 @@
dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x03,0x20,0x80,0x52] dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x03,0x20,0x80,0x52]
ssnop # WARNING: [[@LINE]]:9: warning: ssnop is deprecated for MIPS64r6 and is equivalent to a nop instruction ssnop # WARNING: [[@LINE]]:9: warning: ssnop is deprecated for MIPS64r6 and is equivalent to a nop instruction
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]