[AVR] Fix the test suite

A bunch of tests failed because memory operations have been reordered.

I am unsure which commit changed this behaviour as the AVR build was
failing at that point with an unrelated error.

This commit just reoders some of the CHECK lines in some tests to suit
current llc output.

llvm-svn: 300682

llvm/test/CodeGen/AVR/alloca.ll

@@ -45,14 +45,14 @@ entry:
 define i16 @alloca_write(i16 %x) {
 entry:
 ; CHECK-LABEL: alloca_write:
+; Small offset here
+; CHECK: std Y+23, {{.*}}
+; CHECK: std Y+24, {{.*}}
 ; Big offset here
 ; CHECK: adiw r28, 57
 ; CHECK: std Y+62, {{.*}}
 ; CHECK: std Y+63, {{.*}}
 ; CHECK: sbiw r28, 57
-; Small offset here
-; CHECK: std Y+23, {{.*}}
-; CHECK: std Y+24, {{.*}}
   %p = alloca [15 x i16]
   %k = alloca [14 x i16]
   %arrayidx = getelementptr inbounds [15 x i16], [15 x i16]* %p, i16 0, i16 45

llvm/test/CodeGen/AVR/call.ll

@@ -30,9 +30,9 @@ define i8 @calli8_reg() {
 
 define i8 @calli8_stack() {
 ; CHECK-LABEL: calli8_stack:
-; CHECK: ldi [[REG1:r[0-9]+]], 11
+; CHECK: ldi [[REG1:r[0-9]+]], 10
 ; CHECK: push [[REG1]]
-; CHECK: ldi [[REG1]], 10
+; CHECK: ldi [[REG1]], 11
 ; CHECK: push [[REG1]]
 ; CHECK: call foo8_3
     %result1 = call i8 @foo8_3(i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11)
@@ -52,14 +52,14 @@ define i16 @calli16_reg() {
 
 define i16 @calli16_stack() {
 ; CHECK-LABEL: calli16_stack:
-; CHECK: ldi [[REG1:r[0-9]+]], 10
-; CHECK: ldi [[REG2:r[0-9]+]], 2
-; CHECK: push [[REG2]]
-; CHECK: push [[REG1]]
 ; CHECK: ldi [[REG1:r[0-9]+]], 9
 ; CHECK: ldi [[REG2:r[0-9]+]], 2 
 ; CHECK: push [[REG2]]
 ; CHECK: push [[REG1]]
+; CHECK: ldi [[REG1:r[0-9]+]], 10
+; CHECK: ldi [[REG2:r[0-9]+]], 2
+; CHECK: push [[REG2]]
+; CHECK: push [[REG1]]
 ; CHECK: call foo16_2
     %result1 = call i16 @foo16_2(i16 512, i16 513, i16 514, i16 515, i16 516, i16 517, i16 518, i16 519, i16 520, i16 521, i16 522)
     ret i16 %result1
@@ -82,14 +82,14 @@ define i32 @calli32_reg() {
 
 define i32 @calli32_stack() {
 ; CHECK-LABEL: calli32_stack:
-; CHECK: ldi [[REG1:r[0-9]+]], 15
-; CHECK: ldi [[REG2:r[0-9]+]], 2
-; CHECK: push [[REG2]]
-; CHECK: push [[REG1]]
 ; CHECK: ldi [[REG1:r[0-9]+]], 64
 ; CHECK: ldi [[REG2:r[0-9]+]], 66
 ; CHECK: push [[REG2]]
 ; CHECK: push [[REG1]]
+; CHECK: ldi [[REG1:r[0-9]+]], 15
+; CHECK: ldi [[REG2:r[0-9]+]], 2
+; CHECK: push [[REG2]]
+; CHECK: push [[REG1]]
 ; CHECK: call foo32_2
     %result1 = call i32 @foo32_2(i32 1, i32 2, i32 3, i32 4, i32 34554432)
     ret i32 %result1
@@ -112,14 +112,15 @@ define i64 @calli64_reg() {
 
 define i64 @calli64_stack() {
 ; CHECK-LABEL: calli64_stack:
-; CHECK: ldi [[REG1:r[0-9]+]], 31
-; CHECK: ldi [[REG2:r[0-9]+]], 242
-; CHECK: push [[REG2]]
-; CHECK: push [[REG1]]
+
 ; CHECK: ldi [[REG1:r[0-9]+]], 76
 ; CHECK: ldi [[REG2:r[0-9]+]], 73
 ; CHECK: push [[REG2]]
 ; CHECK: push [[REG1]]
+; CHECK: ldi [[REG1:r[0-9]+]], 31
+; CHECK: ldi [[REG2:r[0-9]+]], 242
+; CHECK: push [[REG2]]
+; CHECK: push [[REG1]]
 ; CHECK: ldi [[REG1:r[0-9]+]], 155
 ; CHECK: ldi [[REG2:r[0-9]+]], 88
 ; CHECK: push [[REG2]]

llvm/test/CodeGen/AVR/directmem.ll

@@ -33,10 +33,10 @@ define i8 @global8_load() {
 
 define void @array8_store() {
 ; CHECK-LABEL: array8_store:
-; CHECK: ldi [[REG1:r[0-9]+]], 1
-; CHECK: sts char.array, [[REG1]]
 ; CHECK: ldi [[REG2:r[0-9]+]], 2
 ; CHECK: sts char.array+1, [[REG2]]
+; CHECK: ldi [[REG1:r[0-9]+]], 1
+; CHECK: sts char.array, [[REG1]]
 ; CHECK: ldi [[REG:r[0-9]+]], 3
 ; CHECK: sts char.array+2, [[REG]]
   store i8 1, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @char.array, i32 0, i64 0)
@@ -83,14 +83,18 @@ define i16 @global16_load() {
 
 define void @array16_store() {
 ; CHECK-LABEL: array16_store:
-; CHECK: ldi [[REG1:r[0-9]+]], 187
-; CHECK: ldi [[REG2:r[0-9]+]], 170
-; CHECK: sts int.array+1, [[REG2]]
-; CHECK: sts int.array, [[REG1]]
+
 ; CHECK: ldi [[REG1:r[0-9]+]], 204
 ; CHECK: ldi [[REG2:r[0-9]+]], 170
 ; CHECK: sts int.array+3, [[REG2]]
 ; CHECK: sts int.array+2, [[REG1]]
+
+; CHECK: ldi [[REG1:r[0-9]+]], 187
+; CHECK: ldi [[REG2:r[0-9]+]], 170
+; CHECK: sts int.array+1, [[REG2]]
+; CHECK: sts int.array, [[REG1]]
+
+
 ; CHECK: ldi [[REG1:r[0-9]+]], 221
 ; CHECK: ldi [[REG2:r[0-9]+]], 170
 ; CHECK: sts int.array+5, [[REG2]]
@@ -148,14 +152,6 @@ define i32 @global32_load() {
 
 define void @array32_store() {
 ; CHECK-LABEL: array32_store:
-; CHECK: ldi [[REG1:r[0-9]+]], 27
-; CHECK: ldi [[REG2:r[0-9]+]], 172
-; CHECK: sts long.array+3, [[REG2]]
-; CHECK: sts long.array+2, [[REG1]]
-; CHECK: ldi [[REG1:r[0-9]+]], 68
-; CHECK: ldi [[REG2:r[0-9]+]], 13
-; CHECK: sts long.array+1, [[REG2]]
-; CHECK: sts long.array, [[REG1]]
 ; CHECK: ldi [[REG1:r[0-9]+]], 102
 ; CHECK: ldi [[REG2:r[0-9]+]], 85
 ; CHECK: sts long.array+7, [[REG2]]
@@ -164,6 +160,14 @@ define void @array32_store() {
 ; CHECK: ldi [[REG2:r[0-9]+]], 119
 ; CHECK: sts long.array+5, [[REG2]]
 ; CHECK: sts long.array+4, [[REG1]]
+; CHECK: ldi [[REG1:r[0-9]+]], 27
+; CHECK: ldi [[REG2:r[0-9]+]], 172
+; CHECK: sts long.array+3, [[REG2]]
+; CHECK: sts long.array+2, [[REG1]]
+; CHECK: ldi [[REG1:r[0-9]+]], 68
+; CHECK: ldi [[REG2:r[0-9]+]], 13
+; CHECK: sts long.array+1, [[REG2]]
+; CHECK: sts long.array, [[REG1]]
 ; CHECK: ldi [[REG1:r[0-9]+]], 170
 ; CHECK: ldi [[REG2:r[0-9]+]], 153
 ; CHECK: sts long.array+11, [[REG2]]

llvm/test/CodeGen/AVR/varargs.ll

@@ -40,14 +40,14 @@ define i16 @varargs2(i8* nocapture %x, ...) {
 declare void @var1223(i16, ...)
 define void @varargcall() {
 ; CHECK-LABEL: varargcall:
-; CHECK: ldi [[REG1:r[0-9]+]], 191
-; CHECK: ldi [[REG2:r[0-9]+]], 223
-; CHECK: push [[REG2]]
-; CHECK: push [[REG1]]
 ; CHECK: ldi [[REG1:r[0-9]+]], 189
 ; CHECK: ldi [[REG2:r[0-9]+]], 205
 ; CHECK: push [[REG2]]
 ; CHECK: push [[REG1]]
+; CHECK: ldi [[REG1:r[0-9]+]], 191
+; CHECK: ldi [[REG2:r[0-9]+]], 223
+; CHECK: push [[REG2]]
+; CHECK: push [[REG1]]
 ; CHECK: ldi [[REG1:r[0-9]+]], 205
 ; CHECK: ldi [[REG2:r[0-9]+]], 171
 ; CHECK: push [[REG2]]