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[mlir] [VectorOps] [integration_test] Sparse matrix times vector (DOT version)
Integration test that illustrates the gather operation with a real-world operation expressed in mostly the Vector dialect. Uses jagged diagonal storage. Reviewed By: bondhugula Differential Revision: https://reviews.llvm.org/D84571
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// RUN: mlir-opt %s -convert-scf-to-std -convert-vector-to-llvm -convert-std-to-llvm | \
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// RUN: mlir-cpu-runner -e entry -entry-point-result=void \
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// RUN: -shared-libs=%mlir_integration_test_dir/libmlir_c_runner_utils%shlibext | \
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// RUN: FileCheck %s
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// Illustrates an 8x8 Sparse Matrix x Vector implemented with only operations
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// of the vector dialect (and some std/scf). Essentially, this example performs
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// the following multiplication:
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//
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// 0 1 2 3 4 5 6 7
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// +------------------------+
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// 0 | 1 0 2 0 0 1 0 1 | | 1 | | 21 |
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// 1 | 1 8 0 0 3 0 1 0 | | 2 | | 39 |
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// 2 | 0 0 1 0 0 2 6 2 | | 3 | | 73 |
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// 3 | 0 3 0 1 0 1 0 1 | x | 4 | = | 24 |
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// 4 | 5 0 0 1 1 1 0 0 | | 5 | | 20 |
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// 5 | 0 3 0 0 2 1 2 0 | | 6 | | 36 |
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// 6 | 4 0 7 0 1 0 1 0 | | 7 | | 37 |
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// 7 | 0 3 0 2 0 0 1 1 | | 8 | | 29 |
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// +------------------------+
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//
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// The sparse storage scheme used is an extended column scheme (also referred
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// to as jagged diagonal, which is essentially a vector friendly variant of
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// the general sparse row-wise scheme (also called compressed row storage),
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// using fixed length vectors and no explicit pointer indexing into the
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// value array to find the rows.
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//
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// The extended column storage for the matrix shown above is as follows.
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//
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// VALUE INDEX
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// +---------+ +---------+
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// 0 | 1 2 1 1 | | 0 2 5 7 |
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// 1 | 1 8 3 1 | | 0 1 4 6 |
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// 2 | 1 2 6 2 | | 2 5 6 7 |
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// 3 | 3 1 1 1 | | 1 3 5 7 |
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// 4 | 5 1 1 1 | | 0 3 4 5 |
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// 5 | 3 2 1 2 | | 1 4 5 6 |
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// 6 | 4 7 1 1 | | 0 2 4 6 |
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// 7 | 3 2 1 1 | | 1 3 6 7 |
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// +---------+ +---------+
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//
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// This example illustrates a DOT version for the operation. Another example
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// in this directory illustrates an effective SAXPY version that operates on the
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// transposed jagged diagonal storage to obtain higher vector lengths.
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#contraction_accesses = [
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affine_map<(i) -> (i)>,
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affine_map<(i) -> (i)>,
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affine_map<(i) -> ()>
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]
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#dot_trait = {
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indexing_maps = #contraction_accesses,
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iterator_types = ["reduction"]
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}
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func @spmv8x8(%AVAL: memref<8xvector<4xf32>>,
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%AIDX: memref<8xvector<4xi32>>, %X: memref<?xf32>, %B: memref<?xf32>) {
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%c0 = constant 0 : index
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%c1 = constant 1 : index
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%cn = constant 8 : index
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%f0 = constant 0.0 : f32
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%mask = vector.constant_mask [4] : vector<4xi1>
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scf.for %i = %c0 to %cn step %c1 {
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%aval = load %AVAL[%i] : memref<8xvector<4xf32>>
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%aidx = load %AIDX[%i] : memref<8xvector<4xi32>>
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%0 = vector.gather %X, %aidx, %mask
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: (memref<?xf32>, vector<4xi32>, vector<4xi1>) -> vector<4xf32>
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%1 = vector.contract #dot_trait %aval, %0, %f0 : vector<4xf32>, vector<4xf32> into f32
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store %1, %B[%i] : memref<?xf32>
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}
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return
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}
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func @entry() {
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%c0 = constant 0 : index
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%c1 = constant 1 : index
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%c2 = constant 2 : index
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%c3 = constant 3 : index
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%c4 = constant 4 : index
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%c5 = constant 5 : index
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%c6 = constant 6 : index
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%c7 = constant 7 : index
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%c8 = constant 8 : index
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%f0 = constant 0.0 : f32
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%f1 = constant 1.0 : f32
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%f2 = constant 2.0 : f32
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%f3 = constant 3.0 : f32
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%f4 = constant 4.0 : f32
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%f5 = constant 5.0 : f32
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%f6 = constant 6.0 : f32
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%f7 = constant 7.0 : f32
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%f8 = constant 8.0 : f32
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%i0 = constant 0 : i32
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%i1 = constant 1 : i32
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%i2 = constant 2 : i32
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%i3 = constant 3 : i32
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%i4 = constant 4 : i32
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%i5 = constant 5 : i32
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%i6 = constant 6 : i32
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%i7 = constant 7 : i32
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//
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// Allocate.
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//
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%AVAL = alloc() {alignment = 64} : memref<8xvector<4xf32>>
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%AIDX = alloc() {alignment = 64} : memref<8xvector<4xi32>>
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%X = alloc(%c8) {alignment = 64} : memref<?xf32>
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%B = alloc(%c8) {alignment = 64} : memref<?xf32>
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//
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// Initialize.
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//
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%vf1 = vector.broadcast %f1 : f32 to vector<4xf32>
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%0 = vector.insert %f2, %vf1[1] : f32 into vector<4xf32>
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store %0, %AVAL[%c0] : memref<8xvector<4xf32>>
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%1 = vector.insert %f8, %vf1[1] : f32 into vector<4xf32>
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%2 = vector.insert %f3, %1[2] : f32 into vector<4xf32>
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store %2, %AVAL[%c1] : memref<8xvector<4xf32>>
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%3 = vector.insert %f2, %vf1[1] : f32 into vector<4xf32>
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%4 = vector.insert %f6, %3[2] : f32 into vector<4xf32>
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%5 = vector.insert %f2, %4[3] : f32 into vector<4xf32>
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store %5, %AVAL[%c2] : memref<8xvector<4xf32>>
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%6 = vector.insert %f3, %vf1[0] : f32 into vector<4xf32>
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store %6, %AVAL[%c3] : memref<8xvector<4xf32>>
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%7 = vector.insert %f5, %vf1[0] : f32 into vector<4xf32>
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store %7, %AVAL[%c4] : memref<8xvector<4xf32>>
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%8 = vector.insert %f3, %vf1[0] : f32 into vector<4xf32>
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%9 = vector.insert %f2, %8[1] : f32 into vector<4xf32>
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%10 = vector.insert %f2, %9[3] : f32 into vector<4xf32>
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store %10, %AVAL[%c5] : memref<8xvector<4xf32>>
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%11 = vector.insert %f4, %vf1[0] : f32 into vector<4xf32>
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%12 = vector.insert %f7, %11[1] : f32 into vector<4xf32>
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store %12, %AVAL[%c6] : memref<8xvector<4xf32>>
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%13 = vector.insert %f3, %vf1[0] : f32 into vector<4xf32>
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%14 = vector.insert %f2, %13[1] : f32 into vector<4xf32>
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store %14, %AVAL[%c7] : memref<8xvector<4xf32>>
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%vi0 = vector.broadcast %i0 : i32 to vector<4xi32>
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%20 = vector.insert %i2, %vi0[1] : i32 into vector<4xi32>
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%21 = vector.insert %i5, %20[2] : i32 into vector<4xi32>
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%22 = vector.insert %i7, %21[3] : i32 into vector<4xi32>
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store %22, %AIDX[%c0] : memref<8xvector<4xi32>>
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%23 = vector.insert %i1, %vi0[1] : i32 into vector<4xi32>
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%24 = vector.insert %i4, %23[2] : i32 into vector<4xi32>
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%25 = vector.insert %i6, %24[3] : i32 into vector<4xi32>
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store %25, %AIDX[%c1] : memref<8xvector<4xi32>>
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%26 = vector.insert %i2, %vi0[0] : i32 into vector<4xi32>
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%27 = vector.insert %i5, %26[1] : i32 into vector<4xi32>
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%28 = vector.insert %i6, %27[2] : i32 into vector<4xi32>
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%29 = vector.insert %i7, %28[3] : i32 into vector<4xi32>
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store %29, %AIDX[%c2] : memref<8xvector<4xi32>>
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%30 = vector.insert %i1, %vi0[0] : i32 into vector<4xi32>
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%31 = vector.insert %i3, %30[1] : i32 into vector<4xi32>
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%32 = vector.insert %i5, %31[2] : i32 into vector<4xi32>
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%33 = vector.insert %i7, %32[3] : i32 into vector<4xi32>
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store %33, %AIDX[%c3] : memref<8xvector<4xi32>>
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%34 = vector.insert %i3, %vi0[1] : i32 into vector<4xi32>
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%35 = vector.insert %i4, %34[2] : i32 into vector<4xi32>
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%36 = vector.insert %i5, %35[3] : i32 into vector<4xi32>
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store %36, %AIDX[%c4] : memref<8xvector<4xi32>>
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%37 = vector.insert %i1, %vi0[0] : i32 into vector<4xi32>
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%38 = vector.insert %i4, %37[1] : i32 into vector<4xi32>
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%39 = vector.insert %i5, %38[2] : i32 into vector<4xi32>
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%40 = vector.insert %i6, %39[3] : i32 into vector<4xi32>
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store %40, %AIDX[%c5] : memref<8xvector<4xi32>>
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%41 = vector.insert %i2, %vi0[1] : i32 into vector<4xi32>
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%42 = vector.insert %i4, %41[2] : i32 into vector<4xi32>
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%43 = vector.insert %i6, %42[3] : i32 into vector<4xi32>
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store %43, %AIDX[%c6] : memref<8xvector<4xi32>>
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%44 = vector.insert %i1, %vi0[0] : i32 into vector<4xi32>
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%45 = vector.insert %i3, %44[1] : i32 into vector<4xi32>
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%46 = vector.insert %i6, %45[2] : i32 into vector<4xi32>
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%47 = vector.insert %i7, %46[3] : i32 into vector<4xi32>
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store %47, %AIDX[%c7] : memref<8xvector<4xi32>>
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scf.for %i = %c0 to %c8 step %c1 {
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%ix = addi %i, %c1 : index
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%kx = index_cast %ix : index to i32
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%fx = sitofp %kx : i32 to f32
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store %fx, %X[%i] : memref<?xf32>
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store %f0, %B[%i] : memref<?xf32>
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}
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//
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// Multiply.
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//
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call @spmv8x8(%AVAL, %AIDX, %X, %B) : (memref<8xvector<4xf32>>,
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memref<8xvector<4xi32>>,
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memref<?xf32>, memref<?xf32>) -> ()
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//
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// Print and verify.
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//
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scf.for %i = %c0 to %c8 step %c1 {
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%aval = load %AVAL[%i] : memref<8xvector<4xf32>>
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vector.print %aval : vector<4xf32>
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}
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scf.for %i = %c0 to %c8 step %c1 {
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%aidx = load %AIDX[%i] : memref<8xvector<4xi32>>
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vector.print %aidx : vector<4xi32>
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}
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scf.for %i = %c0 to %c8 step %c1 {
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%ldb = load %B[%i] : memref<?xf32>
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vector.print %ldb : f32
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}
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//
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// CHECK: ( 1, 2, 1, 1 )
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// CHECK-NEXT: ( 1, 8, 3, 1 )
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// CHECK-NEXT: ( 1, 2, 6, 2 )
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// CHECK-NEXT: ( 3, 1, 1, 1 )
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// CHECK-NEXT: ( 5, 1, 1, 1 )
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// CHECK-NEXT: ( 3, 2, 1, 2 )
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// CHECK-NEXT: ( 4, 7, 1, 1 )
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// CHECK-NEXT: ( 3, 2, 1, 1 )
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//
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// CHECK-NEXT: ( 0, 2, 5, 7 )
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// CHECK-NEXT: ( 0, 1, 4, 6 )
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// CHECK-NEXT: ( 2, 5, 6, 7 )
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// CHECK-NEXT: ( 1, 3, 5, 7 )
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// CHECK-NEXT: ( 0, 3, 4, 5 )
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// CHECK-NEXT: ( 1, 4, 5, 6 )
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// CHECK-NEXT: ( 0, 2, 4, 6 )
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// CHECK-NEXT: ( 1, 3, 6, 7 )
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//
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// CHECK-NEXT: 21
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// CHECK-NEXT: 39
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// CHECK-NEXT: 73
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// CHECK-NEXT: 24
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// CHECK-NEXT: 20
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// CHECK-NEXT: 36
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// CHECK-NEXT: 37
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// CHECK-NEXT: 29
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//
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//
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// Free.
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//
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dealloc %AVAL : memref<8xvector<4xf32>>
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dealloc %AIDX : memref<8xvector<4xi32>>
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dealloc %X : memref<?xf32>
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dealloc %B : memref<?xf32>
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return
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}
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