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[mlir][transform][nfc] typo fix 

fix typo

Reviewed By: nicolasvasilache, ftynse

Differential Revision: https://reviews.llvm.org/D135242
This commit is contained in:
Guray Ozen 2022-10-05 08:48:19 +02:00
parent b1bdcd4d5c
commit 78305720f3
2 changed files with 9 additions and 9 deletions
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10
mlir/include/mlir/Dialect/GPU/TransformOps/GPUTransformOps.h
View File

@ -41,17 +41,17 @@ namespace gpu {
/// predication. Dynamic, `scf.foreach_thread` trip counts are currently not
/// supported. Dynamic block dim sizes are currently not supported.
DiagnosedSilenceableFailure
mapNestedForeachToThreadsImp(RewriterBase &rewriter, Operation *target,
const SmallVectorImpl<int64_t> &blockDim,
bool syncAfterDistribute,
llvm::Optional<TransformOpInterface> transformOp);
mapNestedForeachToThreadsImpl(RewriterBase &rewriter, Operation *target,
const SmallVectorImpl<int64_t> &blockDim,
bool syncAfterDistribute,
llvm::Optional<TransformOpInterface> transformOp);
/// Maps the top level `scf.foreach_thread` op to GPU Thread Blocks. Mapping is
/// one-to-one and the induction variables of `scf.foreach_thread` are rewritten
/// to gpu.block_id according to the thread_dim_apping attribute. Dynamic,
/// `scf.foreach_thread` trip counts are currently not supported. Dynamic block
/// dim sizes are currently not supported.
DiagnosedSilenceableFailure mapForeachToBlocksImp(
DiagnosedSilenceableFailure mapForeachToBlocksImpl(
RewriterBase &rewriter, scf::ForeachThreadOp foreachThreadOp,
function_ref<void(RewriterBase &, scf::ForeachThreadOp,
SmallVectorImpl<Value> &)>

8
mlir/lib/Dialect/GPU/TransformOps/GPUTransformOps.cpp
View File

@ -151,7 +151,7 @@ alterGpuLaunch(SimpleRewriter &rewriter, LaunchOp gpuLaunch,
// MapForeachToBlocks
//===----------------------------------------------------------------------===//
DiagnosedSilenceableFailure mlir::transform::gpu::mapForeachToBlocksImp(
DiagnosedSilenceableFailure mlir::transform::gpu::mapForeachToBlocksImpl(
RewriterBase &rewriter, scf::ForeachThreadOp foreachThreadOp,
function_ref<void(RewriterBase &, scf::ForeachThreadOp,
SmallVectorImpl<Value> &)>
@ -291,7 +291,7 @@ transform::MapForeachToBlocks::applyToOne(Operation *target,
}
SmallVector<int64_t> gridDim = extractFromI64ArrayAttr(getGridDim());
diag = mlir::transform::gpu::mapForeachToBlocksImp(
diag = mlir::transform::gpu::mapForeachToBlocksImpl(
rewriter, topLevelForeachThreadOp, generateGpuBlockIds, gridDim,
transformOp);
if (diag.succeeded()) {
@ -422,7 +422,7 @@ static DiagnosedSilenceableFailure rewriteOneForeachThreadToGpuThreads(
return DiagnosedSilenceableFailure::success();
}
DiagnosedSilenceableFailure mlir::transform::gpu::mapNestedForeachToThreadsImp(
DiagnosedSilenceableFailure mlir::transform::gpu::mapNestedForeachToThreadsImpl(
RewriterBase &rewriter, Operation *target,
const SmallVectorImpl<int64_t> &blockDim, bool syncAfterDistribute,
llvm::Optional<TransformOpInterface> transformOp) {
@ -463,7 +463,7 @@ DiagnosedSilenceableFailure transform::MapNestedForeachToThreads::applyToOne(
SimpleRewriter rewriter(getContext());
rewriter.setInsertionPoint(target);
diag = mlir::transform::gpu::mapNestedForeachToThreadsImp(
diag = mlir::transform::gpu::mapNestedForeachToThreadsImpl(
rewriter, target, blockDim, getSyncAfterDistribute(), llvm::None);
if (diag.succeeded()) {
diag =