forked from OSchip/llvm-project
AMDGPU/GlobalISel: Handle AGPRs used for SGPR operands.
We would still need to waterfall if the value were somehow an AGPR, and also need to explicitly copy to a VGPR.
This commit is contained in:
Matt Arsenault
parent
075a92dea1
commit
77e5a195f8
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@ -847,7 +847,18 @@ bool AMDGPURegisterBankInfo::executeInWaterfallLoop(
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continue;
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}
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LLT OpTy = MRI.getType(Op.getReg());
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Register OpReg = Op.getReg();
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LLT OpTy = MRI.getType(OpReg);
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const RegisterBank *OpBank = getRegBank(OpReg, MRI, *TRI);
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if (OpBank != &AMDGPU::VGPRRegBank) {
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// Insert copy from AGPR to VGPR before the loop.
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B.setMBB(MBB);
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OpReg = B.buildCopy(OpTy, OpReg).getReg(0);
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MRI.setRegBank(OpReg, AMDGPU::VGPRRegBank);
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B.setInstr(*I);
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}
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unsigned OpSize = OpTy.getSizeInBits();
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// Can only do a readlane of 32-bit pieces.
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@ -857,11 +868,11 @@ bool AMDGPURegisterBankInfo::executeInWaterfallLoop(
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= MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
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MRI.setType(CurrentLaneOpReg, OpTy);
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constrainGenericRegister(Op.getReg(), AMDGPU::VGPR_32RegClass, MRI);
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constrainGenericRegister(OpReg, AMDGPU::VGPR_32RegClass, MRI);
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// Read the next variant <- also loop target.
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BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32),
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CurrentLaneOpReg)
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.addReg(Op.getReg());
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.addReg(OpReg);
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Register NewCondReg = MRI.createVirtualRegister(WaveRC);
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bool First = CondReg == AMDGPU::NoRegister;
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@ -872,7 +883,7 @@ bool AMDGPURegisterBankInfo::executeInWaterfallLoop(
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B.buildInstr(AMDGPU::V_CMP_EQ_U32_e64)
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.addDef(NewCondReg)
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.addReg(CurrentLaneOpReg)
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.addReg(Op.getReg());
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.addReg(OpReg);
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Op.setReg(CurrentLaneOpReg);
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if (!First) {
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@ -904,7 +915,7 @@ bool AMDGPURegisterBankInfo::executeInWaterfallLoop(
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// Insert the unmerge before the loop.
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B.setMBB(MBB);
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auto Unmerge = B.buildUnmerge(UnmergeTy, Op.getReg());
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auto Unmerge = B.buildUnmerge(UnmergeTy, OpReg);
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B.setInstr(*I);
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unsigned NumPieces = Unmerge->getNumOperands() - 1;
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@ -1048,7 +1059,7 @@ bool AMDGPURegisterBankInfo::collectWaterfallOperands(
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assert(MI.getOperand(Op).isUse());
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Register Reg = MI.getOperand(Op).getReg();
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const RegisterBank *OpBank = getRegBank(Reg, MRI, *TRI);
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if (OpBank->getID() == AMDGPU::VGPRRegBankID)
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if (OpBank->getID() != AMDGPU::SGPRRegBankID)
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SGPROperandRegs.insert(Reg);
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}
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@ -1083,16 +1094,24 @@ void AMDGPURegisterBankInfo::constrainOpWithReadfirstlane(
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MachineInstr &MI, MachineRegisterInfo &MRI, unsigned OpIdx) const {
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Register Reg = MI.getOperand(OpIdx).getReg();
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const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI);
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if (Bank != &AMDGPU::VGPRRegBank)
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if (Bank == &AMDGPU::SGPRRegBank)
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return;
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LLT Ty = MRI.getType(Reg);
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MachineIRBuilder B(MI);
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if (Bank != &AMDGPU::VGPRRegBank) {
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// We need to copy from AGPR to VGPR
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Reg = B.buildCopy(Ty, Reg).getReg(0);
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MRI.setRegBank(Reg, AMDGPU::VGPRRegBank);
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}
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Register SGPR = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
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B.buildInstr(AMDGPU::V_READFIRSTLANE_B32)
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.addDef(SGPR)
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.addReg(Reg);
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MRI.setType(SGPR, MRI.getType(Reg));
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MRI.setType(SGPR, Ty);
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const TargetRegisterClass *Constrained =
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constrainGenericRegister(Reg, AMDGPU::VGPR_32RegClass, MRI);
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@ -1922,7 +1941,7 @@ bool AMDGPURegisterBankInfo::foldExtractEltToCmpSelect(
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const RegisterBank &IdxBank =
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*OpdMapper.getInstrMapping().getOperandMapping(2).BreakDown[0].RegBank;
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bool IsDivergentIdx = IdxBank == AMDGPU::VGPRRegBank;
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bool IsDivergentIdx = IdxBank != AMDGPU::SGPRRegBank;
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LLT VecTy = MRI.getType(VecReg);
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unsigned EltSize = VecTy.getScalarSizeInBits();
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@ -2004,7 +2023,7 @@ bool AMDGPURegisterBankInfo::foldInsertEltToCmpSelect(
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const RegisterBank &IdxBank =
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*OpdMapper.getInstrMapping().getOperandMapping(3).BreakDown[0].RegBank;
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bool IsDivergentIdx = IdxBank == AMDGPU::VGPRRegBank;
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bool IsDivergentIdx = IdxBank != AMDGPU::SGPRRegBank;
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LLT VecTy = MRI.getType(VecReg);
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unsigned EltSize = VecTy.getScalarSizeInBits();
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@ -1,6 +1,6 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
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# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
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# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
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---
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name: readlane_ss
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@ -69,3 +69,78 @@ body: |
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%1:_(s32) = COPY $vgpr0
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%2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), %0, %1
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...
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---
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name: readlane_aa
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legalized: true
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body: |
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bb.0:
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liveins: $agpr0, $agpr1
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; CHECK-LABEL: name: readlane_aa
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; CHECK: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
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; CHECK: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr1
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; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
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; CHECK: [[COPY3:%[0-9]+]]:vgpr_32(s32) = COPY [[COPY1]](s32)
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; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[COPY3]](s32), implicit $exec
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; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), [[COPY2]](s32), [[V_READFIRSTLANE_B32_]](s32)
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; CHECK: S_ENDPGM 0, implicit [[INT]](s32)
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%0:_(s32) = COPY $agpr0
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%1:_(s32) = COPY $agpr1
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%2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: readlane_as
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legalized: true
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body: |
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bb.0:
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liveins: $agpr0, $sgpr0
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; CHECK-LABEL: name: readlane_as
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; CHECK: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
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; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
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; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), [[COPY2]](s32), [[COPY1]](s32)
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%0:_(s32) = COPY $agpr0
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%1:_(s32) = COPY $sgpr0
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%2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), %0, %1
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...
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---
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name: readlane_sa
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legalized: true
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body: |
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bb.0:
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liveins: $agpr0, $sgpr0
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; CHECK-LABEL: name: readlane_sa
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; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr0
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; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
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; CHECK: [[COPY3:%[0-9]+]]:vgpr_32(s32) = COPY [[COPY1]](s32)
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; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[COPY3]](s32), implicit $exec
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; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), [[COPY2]](s32), [[V_READFIRSTLANE_B32_]](s32)
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = COPY $agpr0
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%2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), %0, %1
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...
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---
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name: readlane_va
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legalized: true
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body: |
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bb.0:
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liveins: $vgpr0, $agpr0
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; CHECK-LABEL: name: readlane_va
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr0
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; CHECK: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY [[COPY1]](s32)
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; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[COPY2]](s32), implicit $exec
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; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), [[COPY]](s32), [[V_READFIRSTLANE_B32_]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $agpr0
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%2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), %0, %1
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...
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@ -0,0 +1,107 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -verify-machineinstrs -run-pass=regbankselect -o - %s | FileCheck %s
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# Make sure that an arbitrary AGPR is treated as a divergent value
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# that needs to be copied to VGPR, and then waterfalled
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# 32-bit case
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---
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name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__agpr_soffset
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $vgpr0, $vgpr1, $agpr0
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; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__agpr_soffset
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $vgpr0, $vgpr1, $agpr0
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; CHECK: %val:vgpr(s32) = COPY $vgpr0
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; CHECK: %rsrc:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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; CHECK: %agpr:agpr(s32) = COPY $agpr0
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; CHECK: %voffset:vgpr(s32) = COPY $vgpr1
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; CHECK: %zero:sgpr(s32) = G_CONSTANT i32 0
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY %zero(s32)
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; CHECK: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
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; CHECK: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY %agpr(s32)
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; CHECK: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
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; CHECK: .1:
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; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; CHECK: [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF]], %bb.0, %9, %bb.1
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; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[COPY1]](s32), implicit $exec
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; CHECK: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_]](s32), [[COPY1]](s32), implicit $exec
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; CHECK: G_AMDGPU_BUFFER_STORE %val(s32), %rsrc(<4 x s32>), [[COPY]](s32), %voffset, [[V_READFIRSTLANE_B32_]], 0, 0, 0 :: (dereferenceable store 4, addrspace 4)
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; CHECK: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[V_CMP_EQ_U32_e64_]], implicit-def $exec, implicit-def $scc, implicit $exec
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; CHECK: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
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; CHECK: S_CBRANCH_EXECNZ %bb.1, implicit $exec
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; CHECK: .2:
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; CHECK: successors: %bb.3(0x80000000)
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; CHECK: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
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; CHECK: .3:
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; CHECK: S_ENDPGM 0
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%val:_(s32) = COPY $vgpr0
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%rsrc:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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%agpr:_(s32) = COPY $agpr0
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%voffset:_(s32) = COPY $vgpr1
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%zero:_(s32) = G_CONSTANT i32 0
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G_AMDGPU_BUFFER_STORE %val, %rsrc, %zero, %voffset, %agpr, 0, 0, 0 :: (dereferenceable store 4, addrspace 4)
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S_ENDPGM 0
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...
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# Register tuple case
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---
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name: load_1d_vgpr_vaddr__agpr_srsrc
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7, $vgpr0
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; CHECK-LABEL: name: load_1d_vgpr_vaddr__agpr_srsrc
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: liveins: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7, $vgpr0
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; CHECK: [[COPY:%[0-9]+]]:agpr(<8 x s32>) = COPY $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[DEF:%[0-9]+]]:vgpr(<4 x s32>) = G_IMPLICIT_DEF
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; CHECK: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
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; CHECK: [[COPY2:%[0-9]+]]:vgpr(<8 x s32>) = COPY [[COPY]](<8 x s32>)
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; CHECK: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64), [[UV2:%[0-9]+]]:vreg_64(s64), [[UV3:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[COPY2]](<8 x s32>)
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; CHECK: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
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; CHECK: .1:
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; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; CHECK: [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF1]], %bb.0, %8, %bb.1
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; CHECK: [[PHI1:%[0-9]+]]:vgpr(<4 x s32>) = G_PHI [[DEF]](<4 x s32>), %bb.0, %2(<4 x s32>), %bb.1
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; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV]].sub0(s64), implicit $exec
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; CHECK: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV]].sub1(s64), implicit $exec
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; CHECK: [[MV:%[0-9]+]]:sreg_64_xexec(s64) = G_MERGE_VALUES [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32)
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; CHECK: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[MV]](s64), [[UV]](s64), implicit $exec
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; CHECK: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV1]].sub0(s64), implicit $exec
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; CHECK: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV1]].sub1(s64), implicit $exec
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; CHECK: [[MV1:%[0-9]+]]:sreg_64_xexec(s64) = G_MERGE_VALUES [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32)
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; CHECK: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[MV1]](s64), [[UV1]](s64), implicit $exec
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; CHECK: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
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; CHECK: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV2]].sub0(s64), implicit $exec
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; CHECK: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV2]].sub1(s64), implicit $exec
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; CHECK: [[MV2:%[0-9]+]]:sreg_64_xexec(s64) = G_MERGE_VALUES [[V_READFIRSTLANE_B32_4]](s32), [[V_READFIRSTLANE_B32_5]](s32)
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; CHECK: [[V_CMP_EQ_U64_e64_2:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[MV2]](s64), [[UV2]](s64), implicit $exec
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; CHECK: [[S_AND_B64_1:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_2]], [[S_AND_B64_]], implicit-def $scc
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; CHECK: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV3]].sub0(s64), implicit $exec
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; CHECK: [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV3]].sub1(s64), implicit $exec
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; CHECK: [[MV3:%[0-9]+]]:sreg_64_xexec(s64) = G_MERGE_VALUES [[V_READFIRSTLANE_B32_6]](s32), [[V_READFIRSTLANE_B32_7]](s32)
|
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; CHECK: [[V_CMP_EQ_U64_e64_3:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[MV3]](s64), [[UV3]](s64), implicit $exec
|
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; CHECK: [[S_AND_B64_2:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_3]], [[S_AND_B64_1]], implicit-def $scc
|
||||
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<8 x s32>) = G_BUILD_VECTOR [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32), [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32), [[V_READFIRSTLANE_B32_4]](s32), [[V_READFIRSTLANE_B32_5]](s32), [[V_READFIRSTLANE_B32_6]](s32), [[V_READFIRSTLANE_B32_7]](s32)
|
||||
; CHECK: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[COPY1]](s32), [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load 16)
|
||||
; CHECK: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_2]], implicit-def $exec, implicit-def $scc, implicit $exec
|
||||
; CHECK: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
|
||||
; CHECK: S_CBRANCH_EXECNZ %bb.1, implicit $exec
|
||||
; CHECK: .2:
|
||||
; CHECK: successors: %bb.3(0x80000000)
|
||||
; CHECK: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK: .3:
|
||||
; CHECK: S_ENDPGM 0, implicit [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
|
||||
%0:_(<8 x s32>) = COPY $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
|
||||
%1:_(s32) = COPY $vgpr0
|
||||
%2:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, %1(s32), %0(<8 x s32>), 0, 0, 0 :: (dereferenceable load 16)
|
||||
S_ENDPGM 0, implicit %2
|
||||
...
|
||||
Loading…
Reference in New Issue