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Fix register names, fix register allocation order, handle frame pointer. 

llvm-svn: 70701
This commit is contained in:
Anton Korobeynikov 2009-05-03 12:59:16 +00:00
parent 64717bbc14
commit 77e5a11ec2
2 changed files with 21 additions and 11 deletions
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2
llvm/lib/Target/MSP430/MSP430RegisterInfo.cpp
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@ -15,6 +15,8 @@
#include "MSP430.h" #include "MSP430.h"
#include "MSP430RegisterInfo.h" #include "MSP430RegisterInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/ADT/BitVector.h" #include "llvm/ADT/BitVector.h"
using namespace llvm; using namespace llvm;

30
llvm/lib/Target/MSP430/MSP430RegisterInfo.td
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@ -20,11 +20,11 @@ class MSP430Reg<bits<4> num, string n> : Register<n> {
// Registers // Registers
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def PC : MSP430Reg<0, "PC">; def PC : MSP430Reg<0, "R0">;
def SP : MSP430Reg<1, "SP">; def SP : MSP430Reg<1, "R1">;
def SR : MSP430Reg<2, "SR">; def SR : MSP430Reg<2, "R2">;
def CG : MSP430Reg<3, "CG">; def CG : MSP430Reg<3, "R3">;
def R4 : MSP430Reg<4, "R4">; def FP : MSP430Reg<4, "R4">;
def R5 : MSP430Reg<5, "R5">; def R5 : MSP430Reg<5, "R5">;
def R6 : MSP430Reg<6, "R6">; def R6 : MSP430Reg<6, "R6">;
def R7 : MSP430Reg<7, "R7">; def R7 : MSP430Reg<7, "R7">;
@ -38,10 +38,12 @@ def R14 : MSP430Reg<14, "R14">;
def R15 : MSP430Reg<15, "R15">; def R15 : MSP430Reg<15, "R15">;
def MSP430Regs : RegisterClass<"MSP430", [i16], 16, def MSP430Regs : RegisterClass<"MSP430", [i16], 16,
// Volatile registers // Volatile registers
[R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, [R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
// Volatile, but not allocable // Frame pointer, sometimes allocable
PC, SP, SR, CG]> FP,
// Volatile, but not allocable
PC, SP, SR, CG]>
{ {
let MethodProtos = [{ let MethodProtos = [{
iterator allocation_order_end(const MachineFunction &MF) const; iterator allocation_order_end(const MachineFunction &MF) const;
@ -49,8 +51,14 @@ def MSP430Regs : RegisterClass<"MSP430", [i16], 16,
let MethodBodies = [{ let MethodBodies = [{
MSP430RegsClass::iterator MSP430RegsClass::iterator
MSP430RegsClass::allocation_order_end(const MachineFunction &MF) const { MSP430RegsClass::allocation_order_end(const MachineFunction &MF) const {
// The last 4 registers on the list above are reserved const TargetMachine &TM = MF.getTarget();
return end()-4; const TargetRegisterInfo *RI = TM.getRegisterInfo();
// Depending on whether the function uses frame pointer or not, last 5 or 4
// registers on the list above are reserved
if (RI->hasFP(MF))
return end()-5;
else
return end()-4;
} }
}]; }];
} }