forked from OSchip/llvm-project
AMDGPU/GlobalISel: Select llvm.amdgcn.class
Also fixes missing SubtargetPredicate on f16 class instructions. llvm-svn: 371436
This commit is contained in:
Matt Arsenault
parent
d6c1f5bb15
commit
77e3e9cafd
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@ -34,6 +34,10 @@ def gi_vop3omods :
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GIComplexOperandMatcher<s32, "selectVOP3OMods">,
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GIComplexPatternEquiv<VOP3OMods>;
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def gi_vop3omods0clamp0omod :
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GIComplexOperandMatcher<s32, "selectVOP3Mods0Clamp0OMod">,
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GIComplexPatternEquiv<VOP3Mods0Clamp0OMod>;
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def gi_vop3opselmods0 :
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GIComplexOperandMatcher<s32, "selectVOP3OpSelMods0">,
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GIComplexPatternEquiv<VOP3OpSelMods0>;
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@ -141,7 +141,7 @@ def AMDGPUfp_to_f16 : SDNode<"AMDGPUISD::FP_TO_FP16" , SDTFPToIntOp>;
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def AMDGPUfp16_zext : SDNode<"AMDGPUISD::FP16_ZEXT" , SDTFPToIntOp>;
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def AMDGPUfp_class : SDNode<"AMDGPUISD::FP_CLASS", AMDGPUFPClassOp>;
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def AMDGPUfp_class_impl : SDNode<"AMDGPUISD::FP_CLASS", AMDGPUFPClassOp>;
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// out = max(a, b) a and b are floats, where a nan comparison fails.
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// This is not commutative because this gives the second operand:
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@ -438,6 +438,10 @@ def AMDGPUldexp : PatFrags<(ops node:$src0, node:$src1),
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[(int_amdgcn_ldexp node:$src0, node:$src1),
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(AMDGPUldexp_impl node:$src0, node:$src1)]>;
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def AMDGPUfp_class : PatFrags<(ops node:$src0, node:$src1),
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[(int_amdgcn_class node:$src0, node:$src1),
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(AMDGPUfp_class_impl node:$src0, node:$src1)]>;
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def AMDGPUfmed3 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
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[(int_amdgcn_fmed3 node:$src0, node:$src1, node:$src2),
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(AMDGPUfmed3_impl node:$src0, node:$src1, node:$src2)]>;
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@ -1479,6 +1479,24 @@ AMDGPUInstructionSelector::selectVOP3Mods0(MachineOperand &Root) const {
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[=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod
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}};
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}
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InstructionSelector::ComplexRendererFns
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AMDGPUInstructionSelector::selectVOP3Mods0Clamp0OMod(MachineOperand &Root) const {
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MachineRegisterInfo &MRI
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= Root.getParent()->getParent()->getParent()->getRegInfo();
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Register Src;
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unsigned Mods;
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std::tie(Src, Mods) = selectVOP3ModsImpl(Root.getReg(), MRI);
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return {{
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[=](MachineInstrBuilder &MIB) { MIB.addReg(Src); },
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[=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }, // src0_mods
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[=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // clamp
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[=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod
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}};
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}
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InstructionSelector::ComplexRendererFns
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AMDGPUInstructionSelector::selectVOP3OMods(MachineOperand &Root) const {
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return {{
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@ -110,6 +110,8 @@ private:
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InstructionSelector::ComplexRendererFns
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selectVOP3Mods0(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectVOP3Mods0Clamp0OMod(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectVOP3OMods(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectVOP3Mods(MachineOperand &Root) const;
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@ -738,8 +738,11 @@ defm V_CMP_CLASS_F32 : VOPC_CLASS_F32 <"v_cmp_class_f32">;
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defm V_CMPX_CLASS_F32 : VOPCX_CLASS_F32 <"v_cmpx_class_f32">;
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defm V_CMP_CLASS_F64 : VOPC_CLASS_F64 <"v_cmp_class_f64">;
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defm V_CMPX_CLASS_F64 : VOPCX_CLASS_F64 <"v_cmpx_class_f64">;
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let SubtargetPredicate = Has16BitInsts in {
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defm V_CMP_CLASS_F16 : VOPC_CLASS_F16 <"v_cmp_class_f16">;
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defm V_CMPX_CLASS_F16 : VOPCX_CLASS_F16 <"v_cmpx_class_f16">;
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}
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//===----------------------------------------------------------------------===//
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// V_ICMPIntrinsic Pattern.
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@ -0,0 +1,173 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE64 %s
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# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE32 %s
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---
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name: class_s32_vcc_sv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; WAVE64-LABEL: name: class_s32_vcc_sv
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; WAVE64: liveins: $sgpr0, $vgpr0
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; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE64: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
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; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
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; WAVE32-LABEL: name: class_s32_vcc_sv
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; WAVE32: liveins: $sgpr0, $vgpr0
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; WAVE32: $vcc_hi = IMPLICIT_DEF
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; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
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; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE32: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
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; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:vgpr(s32) = COPY $vgpr0
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%2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: class_s32_vcc_vs
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; WAVE64-LABEL: name: class_s32_vcc_vs
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; WAVE64: liveins: $sgpr0, $vgpr0
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; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
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; WAVE64: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
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; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
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; WAVE32-LABEL: name: class_s32_vcc_vs
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; WAVE32: liveins: $sgpr0, $vgpr0
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; WAVE32: $vcc_hi = IMPLICIT_DEF
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; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
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; WAVE32: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
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; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr(s32) = COPY $sgpr0
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%2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: class_s32_vcc_vv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; WAVE64-LABEL: name: class_s32_vcc_vv
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; WAVE64: liveins: $vgpr0, $vgpr1
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; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; WAVE64: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
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; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
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; WAVE32-LABEL: name: class_s32_vcc_vv
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; WAVE32: liveins: $vgpr0, $vgpr1
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; WAVE32: $vcc_hi = IMPLICIT_DEF
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; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; WAVE32: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
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; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: class_s64_vcc_sv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1, $vgpr0
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; WAVE64-LABEL: name: class_s64_vcc_sv
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; WAVE64: liveins: $sgpr0_sgpr1, $vgpr0
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; WAVE64: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
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; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE64: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
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; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
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; WAVE32-LABEL: name: class_s64_vcc_sv
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; WAVE32: liveins: $sgpr0_sgpr1, $vgpr0
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; WAVE32: $vcc_hi = IMPLICIT_DEF
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; WAVE32: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
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; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE32: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
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; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
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%0:sgpr(s64) = COPY $sgpr0_sgpr1
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%1:vgpr(s32) = COPY $vgpr0
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%2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: class_s64_vcc_vs
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1, $vgpr0
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; WAVE64-LABEL: name: class_s64_vcc_vs
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; WAVE64: liveins: $sgpr0_sgpr1, $vgpr0
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; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
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; WAVE64: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
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; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
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; WAVE32-LABEL: name: class_s64_vcc_vs
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; WAVE32: liveins: $sgpr0_sgpr1, $vgpr0
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; WAVE32: $vcc_hi = IMPLICIT_DEF
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; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
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; WAVE32: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
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; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
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%0:vgpr(s64) = COPY $vgpr0_vgpr1
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%1:sgpr(s32) = COPY $sgpr0
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%2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: class_s64_vcc_vv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr2
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; WAVE64-LABEL: name: class_s64_vcc_vv
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; WAVE64: liveins: $vgpr0_vgpr1, $vgpr2
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; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; WAVE64: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
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; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
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; WAVE32-LABEL: name: class_s64_vcc_vv
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; WAVE32: liveins: $vgpr0_vgpr1, $vgpr2
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; WAVE32: $vcc_hi = IMPLICIT_DEF
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; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; WAVE32: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
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; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
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%0:vgpr(s64) = COPY $vgpr0_vgpr1
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%1:vgpr(s32) = COPY $vgpr2
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%2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
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S_ENDPGM 0, implicit %2
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...
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@ -0,0 +1,98 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE32 %s
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# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE64 %s
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# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*' %s -o /dev/null 2>&1 | FileCheck -check-prefix=SI-ERR %s
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# SI-ERR-NOT: remark
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# SI-ERR: remark: <unknown>:0:0: cannot select: %3:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2:sgpr(s16), %1:vgpr(s32) (in function: class_s16_vcc_sv)
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# SI-ERR-NEXT: remark: <unknown>:0:0: cannot select: %3:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2:vgpr(s16), %1:sgpr(s32) (in function: class_s16_vcc_vs)
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# SI-ERR-NEXT: remark: <unknown>:0:0: cannot select: %3:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2:vgpr(s16), %1:vgpr(s32) (in function: class_s16_vcc_vv)
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# SI-ERR-NOT: remark
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---
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name: class_s16_vcc_sv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; WAVE32-LABEL: name: class_s16_vcc_sv
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; WAVE32: liveins: $sgpr0, $vgpr0
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; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
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; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE32: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
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; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
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; WAVE64-LABEL: name: class_s16_vcc_sv
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; WAVE64: liveins: $sgpr0, $vgpr0
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; WAVE64: $vcc_hi = IMPLICIT_DEF
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; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE64: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
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; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:vgpr(s32) = COPY $vgpr0
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%2:sgpr(s16) = G_TRUNC %0
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%4:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2, %1
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S_ENDPGM 0, implicit %4
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...
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---
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name: class_s16_vcc_vs
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
|
||||
; WAVE32-LABEL: name: class_s16_vcc_vs
|
||||
; WAVE32: liveins: $sgpr0, $vgpr0
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
|
||||
; WAVE32: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
|
||||
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
|
||||
; WAVE64-LABEL: name: class_s16_vcc_vs
|
||||
; WAVE64: liveins: $sgpr0, $vgpr0
|
||||
; WAVE64: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
|
||||
; WAVE64: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
|
||||
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
|
||||
%0:vgpr(s32) = COPY $vgpr0
|
||||
%1:sgpr(s32) = COPY $sgpr0
|
||||
%2:vgpr(s16) = G_TRUNC %0
|
||||
%4:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2, %1
|
||||
S_ENDPGM 0, implicit %4
|
||||
...
|
||||
|
||||
---
|
||||
name: class_s16_vcc_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
; WAVE32-LABEL: name: class_s16_vcc_vv
|
||||
; WAVE32: liveins: $vgpr0, $vgpr1
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE32: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
|
||||
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
|
||||
; WAVE64-LABEL: name: class_s16_vcc_vv
|
||||
; WAVE64: liveins: $vgpr0, $vgpr1
|
||||
; WAVE64: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE64: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
|
||||
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
|
||||
%0:vgpr(s32) = COPY $vgpr0
|
||||
%1:vgpr(s32) = COPY $vgpr1
|
||||
%2:vgpr(s16) = G_TRUNC %0
|
||||
%4:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2, %1
|
||||
S_ENDPGM 0, implicit %4
|
||||
...
|
||||
Loading…
Reference in New Issue