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ARM scheduling fix: don't guess at implicit operand latency. 

This is a minor drive-by fix with no robust way to unit test.
As an example see neon-div.ll:
SU(16):   %Q8<def> = VMOVLsv4i32 %D17, pred:14, pred:%noreg, %Q8<imp-use,kill>
 val SU(1): Latency=2 Reg=%Q8
...should be latency=1

llvm-svn: 158960
This commit is contained in:
Andrew Trick 2012-06-22 02:50:33 +00:00
parent 3ccb1b8cf9
commit 77d0b88999
1 changed files with 9 additions and 5 deletions
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8
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
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@ -2746,12 +2746,13 @@ ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
unsigned NewUseIdx;
const MachineInstr *NewUseMI = getBundledUseMI(&getRegisterInfo(), UseMI,
Reg, NewUseIdx, UseAdj);
if (NewUseMI) {
if (!NewUseMI)
return -1;
UseMI = NewUseMI;
UseIdx = NewUseIdx;
UseMCID = &UseMI->getDesc();
}
}
if (Reg == ARM::CPSR) {
if (DefMI->getOpcode() == ARM::FMSTAT) {
@ -2778,6 +2779,9 @@ ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
return Latency;
}
if (DefMO.isImplicit() || UseMI->getOperand(UseIdx).isImplicit())
return -1;
unsigned DefAlign = DefMI->hasOneMemOperand()
? (*DefMI->memoperands_begin())->getAlignment() : 0;
unsigned UseAlign = UseMI->hasOneMemOperand()