forked from OSchip/llvm-project
[AArch64] Extra negated shift tests. NFC
This commit is contained in:
David Green
parent
f66b8fdc0a
commit
77ae9b364a
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@ -1,5 +1,5 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
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; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon,+sve | FileCheck %s
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define <2 x i64> @shr64x2(<2 x i64> %a, i64 %b) {
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; CHECK-LABEL: shr64x2:
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@ -144,6 +144,149 @@ entry:
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ret <8 x i8> %shr
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}
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define <2 x i64> @lshr64x2(<2 x i64> %a, i64 %b) {
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; CHECK-LABEL: lshr64x2:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg x8, x0
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; CHECK-NEXT: dup v1.2d, x8
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; CHECK-NEXT: neg v1.2d, v1.2d
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; CHECK-NEXT: ushl v0.2d, v0.2d, v1.2d
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; CHECK-NEXT: ret
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entry:
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%sub = sub nsw i64 0, %b
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%splat.splatinsert = insertelement <2 x i64> poison, i64 %sub, i32 0
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%splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> poison, <2 x i32> zeroinitializer
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%shr = lshr <2 x i64> %a, %splat.splat
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ret <2 x i64> %shr
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}
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define <4 x i32> @lshr32x4(<4 x i32> %a, i32 %b) {
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; CHECK-LABEL: lshr32x4:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg w8, w0
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; CHECK-NEXT: dup v1.4s, w8
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; CHECK-NEXT: neg v1.4s, v1.4s
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; CHECK-NEXT: ushl v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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entry:
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%sub = sub nsw i32 0, %b
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%splat.splatinsert = insertelement <4 x i32> poison, i32 %sub, i32 0
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%splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
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%shr = lshr <4 x i32> %a, %splat.splat
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ret <4 x i32> %shr
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}
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define <4 x i32> @lshr32x4undef(<4 x i32> %a, i32 %b) {
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; CHECK-LABEL: lshr32x4undef:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg w8, w0
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; CHECK-NEXT: dup v1.4s, w8
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; CHECK-NEXT: neg v1.4s, v1.4s
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; CHECK-NEXT: ushl v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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entry:
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%sub = sub nsw i32 0, %b
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%splat.splatinsert = insertelement <4 x i32> poison, i32 %sub, i32 0
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%splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> poison, <4 x i32> <i32 undef, i32 0, i32 0, i32 0>
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%shr = lshr <4 x i32> %a, %splat.splat
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ret <4 x i32> %shr
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}
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define <8 x i16> @lshr16x8(<8 x i16> %a, i16 %b) {
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; CHECK-LABEL: lshr16x8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg w8, w0
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; CHECK-NEXT: dup v1.8h, w8
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; CHECK-NEXT: neg v1.8h, v1.8h
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; CHECK-NEXT: ushl v0.8h, v0.8h, v1.8h
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; CHECK-NEXT: ret
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entry:
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%sub = sub i16 0, %b
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%0 = insertelement <8 x i16> undef, i16 %sub, i32 0
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%sh_prom = shufflevector <8 x i16> %0, <8 x i16> undef, <8 x i32> zeroinitializer
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%shr = lshr <8 x i16> %a, %sh_prom
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ret <8 x i16> %shr
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}
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define <16 x i8> @lshr8x16(<16 x i8> %a, i8 %b) {
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; CHECK-LABEL: lshr8x16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg w8, w0
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; CHECK-NEXT: dup v1.16b, w8
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; CHECK-NEXT: neg v1.16b, v1.16b
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; CHECK-NEXT: ushl v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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entry:
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%sub = sub i8 0, %b
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%0 = insertelement <16 x i8> undef, i8 %sub, i32 0
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%sh_prom = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> zeroinitializer
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%shr = lshr <16 x i8> %a, %sh_prom
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ret <16 x i8> %shr
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}
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define <1 x i64> @lshr64x1(<1 x i64> %a, i64 %b) {
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; CHECK-LABEL: lshr64x1:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg x8, x0
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; CHECK-NEXT: fmov d1, x8
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; CHECK-NEXT: neg d1, d1
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; CHECK-NEXT: ushl d0, d0, d1
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; CHECK-NEXT: ret
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entry:
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%sub = sub nsw i64 0, %b
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%splat.splatinsert = insertelement <1 x i64> poison, i64 %sub, i32 0
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%shr = lshr <1 x i64> %a, %splat.splatinsert
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ret <1 x i64> %shr
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}
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define <2 x i32> @lshr32x2(<2 x i32> %a, i32 %b) {
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; CHECK-LABEL: lshr32x2:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg w8, w0
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; CHECK-NEXT: dup v1.2s, w8
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; CHECK-NEXT: neg v1.2s, v1.2s
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; CHECK-NEXT: ushl v0.2s, v0.2s, v1.2s
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; CHECK-NEXT: ret
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entry:
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%sub = sub nsw i32 0, %b
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%splat.splatinsert = insertelement <2 x i32> poison, i32 %sub, i32 0
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%splat.splat = shufflevector <2 x i32> %splat.splatinsert, <2 x i32> poison, <2 x i32> zeroinitializer
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%shr = lshr <2 x i32> %a, %splat.splat
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ret <2 x i32> %shr
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}
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define <4 x i16> @lshr16x4(<4 x i16> %a, i16 %b) {
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; CHECK-LABEL: lshr16x4:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg w8, w0
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; CHECK-NEXT: dup v1.4h, w8
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; CHECK-NEXT: neg v1.4h, v1.4h
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; CHECK-NEXT: ushl v0.4h, v0.4h, v1.4h
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; CHECK-NEXT: ret
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entry:
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%sub = sub i16 0, %b
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%0 = insertelement <4 x i16> undef, i16 %sub, i32 0
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%sh_prom = shufflevector <4 x i16> %0, <4 x i16> undef, <4 x i32> zeroinitializer
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%shr = lshr <4 x i16> %a, %sh_prom
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ret <4 x i16> %shr
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}
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define <8 x i8> @lshr8x8(<8 x i8> %a, i8 %b) {
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; CHECK-LABEL: lshr8x8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg w8, w0
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; CHECK-NEXT: dup v1.8b, w8
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; CHECK-NEXT: neg v1.8b, v1.8b
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; CHECK-NEXT: ushl v0.8b, v0.8b, v1.8b
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; CHECK-NEXT: ret
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entry:
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%sub = sub i8 0, %b
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%0 = insertelement <8 x i8> undef, i8 %sub, i32 0
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%sh_prom = shufflevector <8 x i8> %0, <8 x i8> undef, <8 x i32> zeroinitializer
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%shr = lshr <8 x i8> %a, %sh_prom
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ret <8 x i8> %shr
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}
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define <2 x i64> @shl64x2(<2 x i64> %a, i64 %b) {
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; CHECK-LABEL: shl64x2:
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; CHECK: // %bb.0: // %entry
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@ -262,3 +405,212 @@ entry:
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%shl = shl <8 x i8> %a, %sh_prom
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ret <8 x i8> %shl
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}
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define <vscale x 2 x i64> @shrn64x2(<vscale x 2 x i64> %a, i64 %b) {
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; CHECK-LABEL: shrn64x2:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg x8, x0
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; CHECK-NEXT: mov z1.d, x8
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: asr z0.d, p0/m, z0.d, z1.d
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; CHECK-NEXT: ret
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entry:
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%sub = sub nsw i64 0, %b
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%splat.splatinsert = insertelement <vscale x 2 x i64> poison, i64 %sub, i32 0
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%splat.splat = shufflevector <vscale x 2 x i64> %splat.splatinsert, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
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%shr = ashr <vscale x 2 x i64> %a, %splat.splat
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ret <vscale x 2 x i64> %shr
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}
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define <vscale x 4 x i32> @shrn32x4(<vscale x 4 x i32> %a, i32 %b) {
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; CHECK-LABEL: shrn32x4:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg w8, w0
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; CHECK-NEXT: mov z1.s, w8
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: asr z0.s, p0/m, z0.s, z1.s
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; CHECK-NEXT: ret
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entry:
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%sub = sub nsw i32 0, %b
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%splat.splatinsert = insertelement <vscale x 4 x i32> poison, i32 %sub, i32 0
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%splat.splat = shufflevector <vscale x 4 x i32> %splat.splatinsert, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
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%shr = ashr <vscale x 4 x i32> %a, %splat.splat
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ret <vscale x 4 x i32> %shr
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}
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define <vscale x 8 x i16> @shrn16x8(<vscale x 8 x i16> %a, i16 %b) {
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; CHECK-LABEL: shrn16x8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg w8, w0
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; CHECK-NEXT: mov z1.h, w8
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; CHECK-NEXT: ptrue p0.h
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; CHECK-NEXT: asr z0.h, p0/m, z0.h, z1.h
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; CHECK-NEXT: ret
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entry:
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%sub = sub i16 0, %b
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%0 = insertelement <vscale x 8 x i16> undef, i16 %sub, i32 0
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%sh_prom = shufflevector <vscale x 8 x i16> %0, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
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%shr = ashr <vscale x 8 x i16> %a, %sh_prom
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ret <vscale x 8 x i16> %shr
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}
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define <vscale x 16 x i8> @shrn8x16(<vscale x 16 x i8> %a, i8 %b) {
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; CHECK-LABEL: shrn8x16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg w8, w0
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; CHECK-NEXT: mov z1.b, w8
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; CHECK-NEXT: ptrue p0.b
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; CHECK-NEXT: asr z0.b, p0/m, z0.b, z1.b
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; CHECK-NEXT: ret
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entry:
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%sub = sub i8 0, %b
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%0 = insertelement <vscale x 16 x i8> undef, i8 %sub, i32 0
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%sh_prom = shufflevector <vscale x 16 x i8> %0, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
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%shr = ashr <vscale x 16 x i8> %a, %sh_prom
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ret <vscale x 16 x i8> %shr
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}
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define <vscale x 2 x i64> @lshrn64x2(<vscale x 2 x i64> %a, i64 %b) {
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; CHECK-LABEL: lshrn64x2:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg x8, x0
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; CHECK-NEXT: mov z1.d, x8
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: lsr z0.d, p0/m, z0.d, z1.d
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; CHECK-NEXT: ret
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entry:
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%sub = sub nsw i64 0, %b
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%splat.splatinsert = insertelement <vscale x 2 x i64> poison, i64 %sub, i32 0
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%splat.splat = shufflevector <vscale x 2 x i64> %splat.splatinsert, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
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%shr = lshr <vscale x 2 x i64> %a, %splat.splat
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ret <vscale x 2 x i64> %shr
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}
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define <vscale x 4 x i32> @lshrn32x4(<vscale x 4 x i32> %a, i32 %b) {
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; CHECK-LABEL: lshrn32x4:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg w8, w0
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; CHECK-NEXT: mov z1.s, w8
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: lsr z0.s, p0/m, z0.s, z1.s
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; CHECK-NEXT: ret
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entry:
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%sub = sub nsw i32 0, %b
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%splat.splatinsert = insertelement <vscale x 4 x i32> poison, i32 %sub, i32 0
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%splat.splat = shufflevector <vscale x 4 x i32> %splat.splatinsert, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
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%shr = lshr <vscale x 4 x i32> %a, %splat.splat
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ret <vscale x 4 x i32> %shr
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}
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define <vscale x 8 x i16> @lshrn16x8(<vscale x 8 x i16> %a, i16 %b) {
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; CHECK-LABEL: lshrn16x8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg w8, w0
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; CHECK-NEXT: mov z1.h, w8
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; CHECK-NEXT: ptrue p0.h
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; CHECK-NEXT: lsr z0.h, p0/m, z0.h, z1.h
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; CHECK-NEXT: ret
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entry:
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%sub = sub i16 0, %b
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%0 = insertelement <vscale x 8 x i16> undef, i16 %sub, i32 0
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%sh_prom = shufflevector <vscale x 8 x i16> %0, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
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%shr = lshr <vscale x 8 x i16> %a, %sh_prom
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ret <vscale x 8 x i16> %shr
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}
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define <vscale x 16 x i8> @lshrn8x16(<vscale x 16 x i8> %a, i8 %b) {
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; CHECK-LABEL: lshrn8x16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg w8, w0
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; CHECK-NEXT: mov z1.b, w8
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; CHECK-NEXT: ptrue p0.b
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; CHECK-NEXT: lsr z0.b, p0/m, z0.b, z1.b
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; CHECK-NEXT: ret
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entry:
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%sub = sub i8 0, %b
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%0 = insertelement <vscale x 16 x i8> undef, i8 %sub, i32 0
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%sh_prom = shufflevector <vscale x 16 x i8> %0, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
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%shr = lshr <vscale x 16 x i8> %a, %sh_prom
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ret <vscale x 16 x i8> %shr
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}
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define <vscale x 2 x i64> @shln64x2(<vscale x 2 x i64> %a, i64 %b) {
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; CHECK-LABEL: shln64x2:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg x8, x0
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; CHECK-NEXT: mov z1.d, x8
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: lsl z0.d, p0/m, z0.d, z1.d
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; CHECK-NEXT: ret
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entry:
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%sub = sub nsw i64 0, %b
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%splat.splatinsert = insertelement <vscale x 2 x i64> poison, i64 %sub, i32 0
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%splat.splat = shufflevector <vscale x 2 x i64> %splat.splatinsert, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
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%shl = shl <vscale x 2 x i64> %a, %splat.splat
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ret <vscale x 2 x i64> %shl
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}
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define <vscale x 4 x i32> @shln32x4(<vscale x 4 x i32> %a, i32 %b) {
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; CHECK-LABEL: shln32x4:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg w8, w0
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; CHECK-NEXT: mov z1.s, w8
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: lsl z0.s, p0/m, z0.s, z1.s
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; CHECK-NEXT: ret
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entry:
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%sub = sub nsw i32 0, %b
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%splat.splatinsert = insertelement <vscale x 4 x i32> poison, i32 %sub, i32 0
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%splat.splat = shufflevector <vscale x 4 x i32> %splat.splatinsert, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
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%shl = shl <vscale x 4 x i32> %a, %splat.splat
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ret <vscale x 4 x i32> %shl
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}
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define <vscale x 8 x i16> @shln16x8(<vscale x 8 x i16> %a, i16 %b) {
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; CHECK-LABEL: shln16x8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg w8, w0
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; CHECK-NEXT: mov z1.h, w8
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; CHECK-NEXT: ptrue p0.h
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; CHECK-NEXT: lsl z0.h, p0/m, z0.h, z1.h
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; CHECK-NEXT: ret
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entry:
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%sub = sub i16 0, %b
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%0 = insertelement <vscale x 8 x i16> undef, i16 %sub, i32 0
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%sh_prom = shufflevector <vscale x 8 x i16> %0, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
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%shl = shl <vscale x 8 x i16> %a, %sh_prom
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ret <vscale x 8 x i16> %shl
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}
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define <vscale x 16 x i8> @shln8x16(<vscale x 16 x i8> %a, i8 %b) {
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; CHECK-LABEL: shln8x16:
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; CHECK: // %bb.0: // %entry
|
||||
; CHECK-NEXT: neg w8, w0
|
||||
; CHECK-NEXT: mov z1.b, w8
|
||||
; CHECK-NEXT: ptrue p0.b
|
||||
; CHECK-NEXT: lsl z0.b, p0/m, z0.b, z1.b
|
||||
; CHECK-NEXT: ret
|
||||
entry:
|
||||
%sub = sub i8 0, %b
|
||||
%0 = insertelement <vscale x 16 x i8> undef, i8 %sub, i32 0
|
||||
%sh_prom = shufflevector <vscale x 16 x i8> %0, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
|
||||
%shl = shl <vscale x 16 x i8> %a, %sh_prom
|
||||
ret <vscale x 16 x i8> %shl
|
||||
}
|
||||
|
||||
define <vscale x 16 x i8> @subsub(<vscale x 16 x i8> %a, i8 %b) {
|
||||
; CHECK-LABEL: subsub:
|
||||
; CHECK: // %bb.0: // %entry
|
||||
; CHECK-NEXT: neg w8, w0
|
||||
; CHECK-NEXT: mov z0.b, w8
|
||||
; CHECK-NEXT: subr z0.b, z0.b, #0 // =0x0
|
||||
; CHECK-NEXT: ret
|
||||
entry:
|
||||
%sub = sub i8 0, %b
|
||||
%0 = insertelement <vscale x 16 x i8> undef, i8 %sub, i32 0
|
||||
%sh_prom = shufflevector <vscale x 16 x i8> %0, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
|
||||
%sub2 = sub <vscale x 16 x i8> zeroinitializer, %sh_prom
|
||||
ret <vscale x 16 x i8> %sub2
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,32 @@
|
|||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon,+sve | FileCheck %s
|
||||
|
||||
define <16 x i8> @subsubii8(<16 x i8> %a, i8 %b) {
|
||||
; CHECK-LABEL: subsubii8:
|
||||
; CHECK: // %bb.0: // %entry
|
||||
; CHECK-NEXT: neg w8, w0
|
||||
; CHECK-NEXT: dup v0.16b, w8
|
||||
; CHECK-NEXT: neg v0.16b, v0.16b
|
||||
; CHECK-NEXT: ret
|
||||
entry:
|
||||
%sub = sub i8 0, %b
|
||||
%0 = insertelement <16 x i8> undef, i8 %sub, i32 0
|
||||
%sh_prom = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> zeroinitializer
|
||||
%sub2 = sub <16 x i8> zeroinitializer, %sh_prom
|
||||
ret <16 x i8> %sub2
|
||||
}
|
||||
|
||||
define <vscale x 16 x i8> @subsubni8(<vscale x 16 x i8> %a, i8 %b) {
|
||||
; CHECK-LABEL: subsubni8:
|
||||
; CHECK: // %bb.0: // %entry
|
||||
; CHECK-NEXT: neg w8, w0
|
||||
; CHECK-NEXT: mov z0.b, w8
|
||||
; CHECK-NEXT: subr z0.b, z0.b, #0 // =0x0
|
||||
; CHECK-NEXT: ret
|
||||
entry:
|
||||
%sub = sub i8 0, %b
|
||||
%0 = insertelement <vscale x 16 x i8> undef, i8 %sub, i32 0
|
||||
%sh_prom = shufflevector <vscale x 16 x i8> %0, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
|
||||
%sub2 = sub <vscale x 16 x i8> zeroinitializer, %sh_prom
|
||||
ret <vscale x 16 x i8> %sub2
|
||||
}
|
||||
Loading…
Reference in New Issue