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Rename the narrow shift right immediate operands to "shr_imm*" operands. Also 

expand the testing of the narrowing shift right instructions.

No functionality change.

llvm-svn: 127193
This commit is contained in:
Bill Wendling 2011-03-07 23:38:41 +00:00
parent 71c380f6c7
commit 77ad1dc56d
6 changed files with 53 additions and 32 deletions
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8
llvm/lib/Target/ARM/ARMCodeEmitter.cpp
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@ -312,11 +312,13 @@ namespace {
unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op) unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op)
const { return 0; } const { return 0; }
unsigned getNarrowShiftRight16Imm(const MachineInstr &MI, unsigned Op) unsigned getShiftRight8Imm(const MachineInstr &MI, unsigned Op)
const { return 0; } const { return 0; }
unsigned getNarrowShiftRight32Imm(const MachineInstr &MI, unsigned Op) unsigned getShiftRight16Imm(const MachineInstr &MI, unsigned Op)
const { return 0; } const { return 0; }
unsigned getNarrowShiftRight64Imm(const MachineInstr &MI, unsigned Op) unsigned getShiftRight32Imm(const MachineInstr &MI, unsigned Op)
const { return 0; }
unsigned getShiftRight64Imm(const MachineInstr &MI, unsigned Op)
const { return 0; } const { return 0; }
/// getMovi32Value - Return binary encoding of operand for movw/movt. If the /// getMovi32Value - Return binary encoding of operand for movw/movt. If the

27
llvm/lib/Target/ARM/ARMInstrFormats.td
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@ -221,20 +221,25 @@ def neg_zero : Operand<i32> {
let PrintMethod = "printNegZeroOperand"; let PrintMethod = "printNegZeroOperand";
} }
// Narrow Shift Right Immediate - A narrow shift right immediate is encoded // Shift Right Immediate - A shift right immediate is encoded differently from
// differently from other shift immediates. The imm6 field is encoded like so: // other shift immediates. The imm6 field is encoded like so:
// //
// 16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0> // Offset Encoding
// 32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0> // 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0>
// 64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0> // 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0>
def nsr16_imm : Operand<i32> { // 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0>
let EncoderMethod = "getNarrowShiftRight16Imm"; // 64 64 - <imm> is encoded in imm6<5:0>
def shr_imm8 : Operand<i32> {
let EncoderMethod = "getShiftRight8Imm";
} }
def nsr32_imm : Operand<i32> { def shr_imm16 : Operand<i32> {
let EncoderMethod = "getNarrowShiftRight32Imm"; let EncoderMethod = "getShiftRight16Imm";
} }
def nsr64_imm : Operand<i32> { def shr_imm32 : Operand<i32> {
let EncoderMethod = "getNarrowShiftRight64Imm"; let EncoderMethod = "getShiftRight32Imm";
}
def shr_imm64 : Operand<i32> {
let EncoderMethod = "getShiftRight64Imm";
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//

6
llvm/lib/Target/ARM/ARMInstrNEON.td
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@ -3154,17 +3154,17 @@ multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
SDNode OpNode> { SDNode OpNode> {
def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin, def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
OpcodeStr, !strconcat(Dt, "16"), OpcodeStr, !strconcat(Dt, "16"),
v8i8, v8i16, nsr16_imm, OpNode> { v8i8, v8i16, shr_imm8, OpNode> {
let Inst{21-19} = 0b001; // imm6 = 001xxx let Inst{21-19} = 0b001; // imm6 = 001xxx
} }
def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin, def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
OpcodeStr, !strconcat(Dt, "32"), OpcodeStr, !strconcat(Dt, "32"),
v4i16, v4i32, nsr32_imm, OpNode> { v4i16, v4i32, shr_imm16, OpNode> {
let Inst{21-20} = 0b01; // imm6 = 01xxxx let Inst{21-20} = 0b01; // imm6 = 01xxxx
} }
def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin, def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
OpcodeStr, !strconcat(Dt, "64"), OpcodeStr, !strconcat(Dt, "64"),
v2i32, v2i64, nsr64_imm, OpNode> { v2i32, v2i64, shr_imm32, OpNode> {
let Inst{21} = 0b1; // imm6 = 1xxxxx let Inst{21} = 0b1; // imm6 = 1xxxxx
} }
} }

32
llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp
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@ -278,12 +278,14 @@ public:
unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op, unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups) const;
unsigned getNarrowShiftRight16Imm(const MCInst &MI, unsigned Op, unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups) const;
unsigned getNarrowShiftRight32Imm(const MCInst &MI, unsigned Op, unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups) const;
unsigned getNarrowShiftRight64Imm(const MCInst &MI, unsigned Op, unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const; SmallVectorImpl<MCFixup> &Fixups) const;
unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const;
unsigned NEONThumb2DataIPostEncoder(const MCInst &MI, unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
unsigned EncodedValue) const; unsigned EncodedValue) const;
@ -1209,23 +1211,29 @@ getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
} }
unsigned ARMMCCodeEmitter:: unsigned ARMMCCodeEmitter::
getNarrowShiftRight16Imm(const MCInst &MI, unsigned Op, getShiftRight8Imm(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups) const {
return 8 - MI.getOperand(Op).getImm(); return 8 - MI.getOperand(Op).getImm();
} }
unsigned ARMMCCodeEmitter:: unsigned ARMMCCodeEmitter::
getNarrowShiftRight32Imm(const MCInst &MI, unsigned Op, getShiftRight16Imm(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups) const {
return 16 - MI.getOperand(Op).getImm(); return 16 - MI.getOperand(Op).getImm();
} }
unsigned ARMMCCodeEmitter:: unsigned ARMMCCodeEmitter::
getNarrowShiftRight64Imm(const MCInst &MI, unsigned Op, getShiftRight32Imm(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups) const {
return 32 - MI.getOperand(Op).getImm(); return 32 - MI.getOperand(Op).getImm();
} }
unsigned ARMMCCodeEmitter::
getShiftRight64Imm(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const {
return 64 - MI.getOperand(Op).getImm();
}
void ARMMCCodeEmitter:: void ARMMCCodeEmitter::
EncodeInstruction(const MCInst &MI, raw_ostream &OS, EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups) const { SmallVectorImpl<MCFixup> &Fixups) const {

5
llvm/test/MC/ARM/neon-shift-encoding.s
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@ -158,5 +158,10 @@
vrshrn.i32 d16, q8, #16 vrshrn.i32 d16, q8, #16
@ CHECK: vrshrn.i64 d16, q8, #32 @ encoding: [0x70,0x08,0xe0,0xf2] @ CHECK: vrshrn.i64 d16, q8, #32 @ encoding: [0x70,0x08,0xe0,0xf2]
vrshrn.i64 d16, q8, #32 vrshrn.i64 d16, q8, #32
@ CHECK: vqrshrn.s16 d16, q8, #4 @ encoding: [0x70,0x09,0xcc,0xf2]
vqrshrn.s16 d16, q8, #4
@ CHECK: vqrshrn.s32 d16, q8, #13 @ encoding: [0x70,0x09,0xd3,0xf2] @ CHECK: vqrshrn.s32 d16, q8, #13 @ encoding: [0x70,0x09,0xd3,0xf2]
vqrshrn.s32 d16, q8, #13 vqrshrn.s32 d16, q8, #13
@ CHECK: vqrshrn.s64 d16, q8, #13 @ encoding: [0x70,0x09,0xf3,0xf2]
vqrshrn.s64 d16, q8, #13

7
llvm/utils/TableGen/EDEmitter.cpp
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@ -598,9 +598,10 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type,
IMM("t2adrlabel"); IMM("t2adrlabel");
IMM("shift_imm"); IMM("shift_imm");
IMM("neon_vcvt_imm32"); IMM("neon_vcvt_imm32");
IMM("nsr16_imm"); IMM("shr_imm8");
IMM("nsr32_imm"); IMM("shr_imm16");
IMM("nsr64_imm"); IMM("shr_imm32");
IMM("shr_imm64");
MISC("brtarget", "kOperandTypeARMBranchTarget"); // ? MISC("brtarget", "kOperandTypeARMBranchTarget"); // ?
MISC("uncondbrtarget", "kOperandTypeARMBranchTarget"); // ? MISC("uncondbrtarget", "kOperandTypeARMBranchTarget"); // ?