From 77ad1dc56dcd64faa3fe718cb4133242ead2f5b0 Mon Sep 17 00:00:00 2001
From: Bill Wendling <isanbard@gmail.com>
Date: Mon, 7 Mar 2011 23:38:41 +0000
Subject: [PATCH] Rename the narrow shift right immediate operands to
"shr_imm*" operands. Also expand the testing of the narrowing shift right
instructions.
No functionality change.
llvm-svn: 127193
---
llvm/lib/Target/ARM/ARMCodeEmitter.cpp | 8 +++---
llvm/lib/Target/ARM/ARMInstrFormats.td | 27 ++++++++++++--------
llvm/lib/Target/ARM/ARMInstrNEON.td | 6 ++---
llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp | 32 +++++++++++++++---------
llvm/test/MC/ARM/neon-shift-encoding.s | 5 ++++
llvm/utils/TableGen/EDEmitter.cpp | 7 +++---
6 files changed, 53 insertions(+), 32 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMCodeEmitter.cpp b/llvm/lib/Target/ARM/ARMCodeEmitter.cpp
index 853f234f8c70..fa7371626f29 100644
--- a/llvm/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/llvm/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -312,11 +312,13 @@ namespace {
unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op)
const { return 0; }
- unsigned getNarrowShiftRight16Imm(const MachineInstr &MI, unsigned Op)
+ unsigned getShiftRight8Imm(const MachineInstr &MI, unsigned Op)
const { return 0; }
- unsigned getNarrowShiftRight32Imm(const MachineInstr &MI, unsigned Op)
+ unsigned getShiftRight16Imm(const MachineInstr &MI, unsigned Op)
const { return 0; }
- unsigned getNarrowShiftRight64Imm(const MachineInstr &MI, unsigned Op)
+ unsigned getShiftRight32Imm(const MachineInstr &MI, unsigned Op)
+ const { return 0; }
+ unsigned getShiftRight64Imm(const MachineInstr &MI, unsigned Op)
const { return 0; }
/// getMovi32Value - Return binary encoding of operand for movw/movt. If the
diff --git a/llvm/lib/Target/ARM/ARMInstrFormats.td b/llvm/lib/Target/ARM/ARMInstrFormats.td
index cf8c4724c59d..1c3476c0a92c 100644
--- a/llvm/lib/Target/ARM/ARMInstrFormats.td
+++ b/llvm/lib/Target/ARM/ARMInstrFormats.td
@@ -221,20 +221,25 @@ def neg_zero : Operand<i32> {
let PrintMethod = "printNegZeroOperand";
}
-// Narrow Shift Right Immediate - A narrow shift right immediate is encoded
-// differently from other shift immediates. The imm6 field is encoded like so:
+// Shift Right Immediate - A shift right immediate is encoded differently from
+// other shift immediates. The imm6 field is encoded like so:
//
-// 16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
-// 32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
-// 64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>
-def nsr16_imm : Operand<i32> {
- let EncoderMethod = "getNarrowShiftRight16Imm";
+// Offset Encoding
+// 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0>
+// 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0>
+// 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0>
+// 64 64 - <imm> is encoded in imm6<5:0>
+def shr_imm8 : Operand<i32> {
+ let EncoderMethod = "getShiftRight8Imm";
}
-def nsr32_imm : Operand<i32> {
- let EncoderMethod = "getNarrowShiftRight32Imm";
+def shr_imm16 : Operand<i32> {
+ let EncoderMethod = "getShiftRight16Imm";
}
-def nsr64_imm : Operand<i32> {
- let EncoderMethod = "getNarrowShiftRight64Imm";
+def shr_imm32 : Operand<i32> {
+ let EncoderMethod = "getShiftRight32Imm";
+}
+def shr_imm64 : Operand<i32> {
+ let EncoderMethod = "getShiftRight64Imm";
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/ARM/ARMInstrNEON.td b/llvm/lib/Target/ARM/ARMInstrNEON.td
index 5be6df5025a8..b979232d4667 100644
--- a/llvm/lib/Target/ARM/ARMInstrNEON.td
+++ b/llvm/lib/Target/ARM/ARMInstrNEON.td
@@ -3154,17 +3154,17 @@ multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
SDNode OpNode> {
def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
OpcodeStr, !strconcat(Dt, "16"),
- v8i8, v8i16, nsr16_imm, OpNode> {
+ v8i8, v8i16, shr_imm8, OpNode> {
let Inst{21-19} = 0b001; // imm6 = 001xxx
}
def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
OpcodeStr, !strconcat(Dt, "32"),
- v4i16, v4i32, nsr32_imm, OpNode> {
+ v4i16, v4i32, shr_imm16, OpNode> {
let Inst{21-20} = 0b01; // imm6 = 01xxxx
}
def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
OpcodeStr, !strconcat(Dt, "64"),
- v2i32, v2i64, nsr64_imm, OpNode> {
+ v2i32, v2i64, shr_imm32, OpNode> {
let Inst{21} = 0b1; // imm6 = 1xxxxx
}
}
diff --git a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp
index 48884a1d7182..10607b17c532 100644
--- a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp
+++ b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp
@@ -278,12 +278,14 @@ public:
unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const;
- unsigned getNarrowShiftRight16Imm(const MCInst &MI, unsigned Op,
- SmallVectorImpl<MCFixup> &Fixups) const;
- unsigned getNarrowShiftRight32Imm(const MCInst &MI, unsigned Op,
- SmallVectorImpl<MCFixup> &Fixups) const;
- unsigned getNarrowShiftRight64Imm(const MCInst &MI, unsigned Op,
- SmallVectorImpl<MCFixup> &Fixups) const;
+ unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
+ SmallVectorImpl<MCFixup> &Fixups) const;
+ unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
+ SmallVectorImpl<MCFixup> &Fixups) const;
+ unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
+ SmallVectorImpl<MCFixup> &Fixups) const;
+ unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
+ SmallVectorImpl<MCFixup> &Fixups) const;
unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
unsigned EncodedValue) const;
@@ -1209,23 +1211,29 @@ getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
}
unsigned ARMMCCodeEmitter::
-getNarrowShiftRight16Imm(const MCInst &MI, unsigned Op,
- SmallVectorImpl<MCFixup> &Fixups) const {
+getShiftRight8Imm(const MCInst &MI, unsigned Op,
+ SmallVectorImpl<MCFixup> &Fixups) const {
return 8 - MI.getOperand(Op).getImm();
}
unsigned ARMMCCodeEmitter::
-getNarrowShiftRight32Imm(const MCInst &MI, unsigned Op,
- SmallVectorImpl<MCFixup> &Fixups) const {
+getShiftRight16Imm(const MCInst &MI, unsigned Op,
+ SmallVectorImpl<MCFixup> &Fixups) const {
return 16 - MI.getOperand(Op).getImm();
}
unsigned ARMMCCodeEmitter::
-getNarrowShiftRight64Imm(const MCInst &MI, unsigned Op,
- SmallVectorImpl<MCFixup> &Fixups) const {
+getShiftRight32Imm(const MCInst &MI, unsigned Op,
+ SmallVectorImpl<MCFixup> &Fixups) const {
return 32 - MI.getOperand(Op).getImm();
}
+unsigned ARMMCCodeEmitter::
+getShiftRight64Imm(const MCInst &MI, unsigned Op,
+ SmallVectorImpl<MCFixup> &Fixups) const {
+ return 64 - MI.getOperand(Op).getImm();
+}
+
void ARMMCCodeEmitter::
EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups) const {
diff --git a/llvm/test/MC/ARM/neon-shift-encoding.s b/llvm/test/MC/ARM/neon-shift-encoding.s
index 1985a6a647dc..3d34de01afad 100644
--- a/llvm/test/MC/ARM/neon-shift-encoding.s
+++ b/llvm/test/MC/ARM/neon-shift-encoding.s
@@ -158,5 +158,10 @@
vrshrn.i32 d16, q8, #16
@ CHECK: vrshrn.i64 d16, q8, #32 @ encoding: [0x70,0x08,0xe0,0xf2]
vrshrn.i64 d16, q8, #32
+
+@ CHECK: vqrshrn.s16 d16, q8, #4 @ encoding: [0x70,0x09,0xcc,0xf2]
+ vqrshrn.s16 d16, q8, #4
@ CHECK: vqrshrn.s32 d16, q8, #13 @ encoding: [0x70,0x09,0xd3,0xf2]
vqrshrn.s32 d16, q8, #13
+@ CHECK: vqrshrn.s64 d16, q8, #13 @ encoding: [0x70,0x09,0xf3,0xf2]
+ vqrshrn.s64 d16, q8, #13
diff --git a/llvm/utils/TableGen/EDEmitter.cpp b/llvm/utils/TableGen/EDEmitter.cpp
index b3deb84f6673..e171da02a2f8 100644
--- a/llvm/utils/TableGen/EDEmitter.cpp
+++ b/llvm/utils/TableGen/EDEmitter.cpp
@@ -598,9 +598,10 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type,
IMM("t2adrlabel");
IMM("shift_imm");
IMM("neon_vcvt_imm32");
- IMM("nsr16_imm");
- IMM("nsr32_imm");
- IMM("nsr64_imm");
+ IMM("shr_imm8");
+ IMM("shr_imm16");
+ IMM("shr_imm32");
+ IMM("shr_imm64");
MISC("brtarget", "kOperandTypeARMBranchTarget"); // ?
MISC("uncondbrtarget", "kOperandTypeARMBranchTarget"); // ?