forked from OSchip/llvm-project
Fix bugs in the pseuo-ization of ADCS/SBCS pointed out by Jim, as well as doing the expansion earlier (using a custom inserter) to allow for the chance of predicating these instructions.
llvm-svn: 128940
This commit is contained in:
Owen Anderson
parent
0cb4acfc8d
commit
77aa266de8
llvm/lib/Target/ARM
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@ -55,7 +55,6 @@ namespace {
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void ExpandVLD(MachineBasicBlock::iterator &MBBI);
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void ExpandVST(MachineBasicBlock::iterator &MBBI);
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void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
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void ExpandSBitOp(MachineBasicBlock::iterator &MBBI);
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void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
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unsigned Opc, bool IsExt, unsigned NumRegs);
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void ExpandMOV32BitImm(MachineBasicBlock &MBB,
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@ -630,43 +629,6 @@ void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
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MI.eraseFromParent();
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}
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void ARMExpandPseudo::ExpandSBitOp(MachineBasicBlock::iterator &MBBI) {
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MachineInstr &MI = *MBBI;
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MachineBasicBlock &MBB = *MI.getParent();
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unsigned OldOpc = MI.getOpcode();
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unsigned Opc = 0;
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switch (OldOpc) {
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case ARM::ADCSSrr:
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Opc = ARM::ADCrr;
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break;
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case ARM::ADCSSri:
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Opc = ARM::ADCri;
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break;
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case ARM::ADCSSrs:
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Opc = ARM::ADCrs;
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break;
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case ARM::SBCSSrr:
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Opc = ARM::SBCrr;
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break;
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case ARM::SBCSSri:
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Opc = ARM::SBCri;
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break;
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case ARM::SBCSSrs:
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Opc = ARM::SBCrs;
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break;
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default:
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llvm_unreachable("Unknown opcode?");
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}
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MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
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MIB.addOperand(MachineOperand::CreateImm(0)); // Predicate
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MIB.addOperand(MachineOperand::CreateImm(0)); // S bit
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for (unsigned i = 0; i < MI.getNumOperands(); ++i)
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MIB.addOperand(MI.getOperand(i));
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TransferImpOps(MI, MIB, MIB);
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MI.eraseFromParent();
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}
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void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI) {
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MachineInstr &MI = *MBBI;
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@ -979,15 +941,6 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
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ExpandMOV32BitImm(MBB, MBBI);
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return true;
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case ARM::ADCSSri:
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case ARM::ADCSSrr:
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case ARM::ADCSSrs:
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case ARM::SBCSSri:
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case ARM::SBCSSrr:
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case ARM::SBCSSrs:
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ExpandSBitOp(MBBI);
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return true;
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case ARM::VMOVQQ: {
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unsigned DstReg = MI.getOperand(0).getReg();
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bool DstIsDead = MI.getOperand(0).isDead();
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@ -5024,6 +5024,48 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
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case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
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case ARM::ADCSSri:
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case ARM::ADCSSrr:
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case ARM::ADCSSrs:
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case ARM::SBCSSri:
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case ARM::SBCSSrr:
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case ARM::SBCSSrs: {
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unsigned OldOpc = MI->getOpcode();
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unsigned Opc = 0;
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switch (OldOpc) {
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case ARM::ADCSSrr:
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Opc = ARM::ADCrr;
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break;
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case ARM::ADCSSri:
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Opc = ARM::ADCri;
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break;
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case ARM::ADCSSrs:
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Opc = ARM::ADCrs;
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break;
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case ARM::SBCSSrr:
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Opc = ARM::SBCrr;
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break;
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case ARM::SBCSSri:
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Opc = ARM::SBCri;
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break;
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case ARM::SBCSSrs:
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Opc = ARM::SBCrs;
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break;
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default:
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llvm_unreachable("Unknown opcode?");
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}
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MachineInstrBuilder MIB =
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BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(Opc));
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for (unsigned i = 0; i < MI->getNumOperands(); ++i)
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MIB.addOperand(MI->getOperand(i));
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AddDefaultPred(MIB);
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MIB.addReg(ARM::CPSR, RegState::Define); // S bit
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MI->eraseFromParent();
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return BB;
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}
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case ARM::tMOVCCr_pseudo: {
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// To "insert" a SELECT_CC instruction, we actually have to insert the
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// diamond control-flow pattern. The incoming instruction knows the
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@ -936,8 +936,7 @@ multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
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}
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// Carry setting variants
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let isCodeGenOnly = 1, Defs = [CPSR] in {
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multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
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bit Commutable = 0> {
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multiclass AI1_adde_sube_s_irs<PatFrag opnode, bit Commutable = 0> {
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def Sri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
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Size4Bytes, IIC_iALUi,
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[(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
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@ -2197,10 +2196,12 @@ defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
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BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
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// ADC and SUBC with 's' bit set.
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defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
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let usesCustomInserter = 1 in {
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defm ADCS : AI1_adde_sube_s_irs<
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BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
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defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
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defm SBCS : AI1_adde_sube_s_irs<
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BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
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}
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def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
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IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
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