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[ARM64][AArch64] Update disassembler attributes to ARMv8.5 ISA with SVE extensions 

This patch updates assembler attributes for AArch64 targets so we can disassemble newer instructions supported in ISA version 8.5 and SVE extensions.

Differential Revision: https://reviews.llvm.org/D62235

llvm-svn: 361451
This commit is contained in:
Omair Javaid 2019-05-23 00:46:34 +00:00
parent ada9d2d884
commit 772176dad1
1 changed files with 3 additions and 3 deletions
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6
lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
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@ -1188,10 +1188,10 @@ DisassemblerLLVMC::DisassemblerLLVMC(const ArchSpec &arch,
features_str += "+dspr2,";
}
// If any AArch64 variant, enable the ARMv8.2 ISA extensions so we can
// disassemble newer instructions.
// If any AArch64 variant, enable the ARMv8.5 ISA with SVE extensions so we
// can disassemble newer instructions.
if (triple.getArch() == llvm::Triple::aarch64)
features_str += "+v8.2a";
features_str += "+v8.5a,+sve2";
if (triple.getArch() == llvm::Triple::aarch64
&& triple.getVendor() == llvm::Triple::Apple) {