forked from OSchip/llvm-project
[llvm] [CodeGen] Fixed vector halving bug for masked store
Summary: Note that this fix is very similar to what has already been done for the masked load in https://reviews.llvm.org/D78608 Bugs: https://bugs.llvm.org/show_bug.cgi?id=45563 https://bugs.llvm.org/show_bug.cgi?id=45833 Reviewers: craig.topper, nicolasvasilache, mehdi_amini Reviewed By: craig.topper Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D79611
This commit is contained in:
aartbik
parent
2ea7187ab9
commit
771d30c647
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@ -2324,13 +2324,9 @@ SDValue DAGTypeLegalizer::SplitVecOp_MSTORE(MaskedStoreSDNode *N,
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assert(Offset.isUndef() && "Unexpected indexed masked store offset");
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assert(Offset.isUndef() && "Unexpected indexed masked store offset");
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SDValue Mask = N->getMask();
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SDValue Mask = N->getMask();
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SDValue Data = N->getValue();
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SDValue Data = N->getValue();
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EVT MemoryVT = N->getMemoryVT();
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Align Alignment = N->getOriginalAlign();
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Align Alignment = N->getOriginalAlign();
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SDLoc DL(N);
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SDLoc DL(N);
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EVT LoMemVT, HiMemVT;
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std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
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SDValue DataLo, DataHi;
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SDValue DataLo, DataHi;
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if (getTypeAction(Data.getValueType()) == TargetLowering::TypeSplitVector)
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if (getTypeAction(Data.getValueType()) == TargetLowering::TypeSplitVector)
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// Split Data operand
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// Split Data operand
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@ -2349,7 +2345,13 @@ SDValue DAGTypeLegalizer::SplitVecOp_MSTORE(MaskedStoreSDNode *N,
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std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, DL);
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std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, DL);
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}
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}
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SDValue Lo, Hi;
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EVT MemoryVT = N->getMemoryVT();
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EVT LoMemVT, HiMemVT;
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bool HiIsEmpty = false;
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std::tie(LoMemVT, HiMemVT) =
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DAG.GetDependentSplitDestVTs(MemoryVT, DataLo.getValueType(), &HiIsEmpty);
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SDValue Lo, Hi, Res;
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MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
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MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
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N->getPointerInfo(), MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
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N->getPointerInfo(), MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
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Alignment, N->getAAInfo(), N->getRanges());
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Alignment, N->getAAInfo(), N->getRanges());
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@ -2358,21 +2360,30 @@ SDValue DAGTypeLegalizer::SplitVecOp_MSTORE(MaskedStoreSDNode *N,
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N->getAddressingMode(), N->isTruncatingStore(),
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N->getAddressingMode(), N->isTruncatingStore(),
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N->isCompressingStore());
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N->isCompressingStore());
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Ptr = TLI.IncrementMemoryAddress(Ptr, MaskLo, DL, LoMemVT, DAG,
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if (HiIsEmpty) {
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N->isCompressingStore());
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// The hi masked store has zero storage size.
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unsigned HiOffset = LoMemVT.getStoreSize();
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// Only the lo masked store is needed.
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Res = Lo;
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} else {
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MMO = DAG.getMachineFunction().getMachineMemOperand(
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Ptr = TLI.IncrementMemoryAddress(Ptr, MaskLo, DL, LoMemVT, DAG,
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N->getPointerInfo().getWithOffset(HiOffset), MachineMemOperand::MOStore,
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N->isCompressingStore());
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HiMemVT.getStoreSize(), Alignment, N->getAAInfo(), N->getRanges());
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unsigned HiOffset = LoMemVT.getStoreSize();
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Hi = DAG.getMaskedStore(Ch, DL, DataHi, Ptr, Offset, MaskHi, HiMemVT, MMO,
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MMO = DAG.getMachineFunction().getMachineMemOperand(
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N->getAddressingMode(), N->isTruncatingStore(),
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N->getPointerInfo().getWithOffset(HiOffset), MachineMemOperand::MOStore,
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N->isCompressingStore());
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HiMemVT.getStoreSize(), Alignment, N->getAAInfo(), N->getRanges());
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// Build a factor node to remember that this store is independent of the
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Hi = DAG.getMaskedStore(Ch, DL, DataHi, Ptr, Offset, MaskHi, HiMemVT, MMO,
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// other one.
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N->getAddressingMode(), N->isTruncatingStore(),
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return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
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N->isCompressingStore());
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// Build a factor node to remember that this store is independent of the
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// other one.
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Res = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
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}
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return Res;
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}
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}
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SDValue DAGTypeLegalizer::SplitVecOp_MSCATTER(MaskedScatterSDNode *N,
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SDValue DAGTypeLegalizer::SplitVecOp_MSCATTER(MaskedScatterSDNode *N,
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@ -0,0 +1,301 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O3 -mtriple=x86_64-linux-generic -mattr=avx < %s | FileCheck %s
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; Bug 45833:
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; The SplitVecRes_MSTORE method should split a extended value type
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; according to the halving of the enveloping type to avoid all sorts
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; of inconsistencies downstream. For example for a extended value type
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; with VL=14 and enveloping type VL=16 that is split 8/8, the extended
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; type should be split 8/6 and not 7/7. This also accounts for hi masked
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; store that get zero storage size (and are unused).
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define void @mstore_split9(<9 x float> %value, <9 x float>* %addr, <9 x i1> %mask) {
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; CHECK-LABEL: mstore_split9:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vinsertps {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[2,3]
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; CHECK-NEXT: vinsertps {{.*#+}} xmm4 = xmm4[0,1],xmm6[0],xmm4[3]
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; CHECK-NEXT: vinsertps {{.*#+}} xmm4 = xmm4[0,1,2],xmm7[0]
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; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
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; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3]
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; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0]
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; CHECK-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0
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; CHECK-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: vmovd %eax, %xmm2
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; CHECK-NEXT: vpslld $31, %xmm2, %xmm2
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; CHECK-NEXT: vmaskmovps %ymm1, %ymm2, 32(%rdi)
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; CHECK-NEXT: vmovd %esi, %xmm1
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; CHECK-NEXT: vpinsrw $1, %edx, %xmm1, %xmm1
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; CHECK-NEXT: vpinsrw $2, %ecx, %xmm1, %xmm1
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; CHECK-NEXT: vpinsrw $3, %r8d, %xmm1, %xmm1
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; CHECK-NEXT: vpmovzxwd {{.*#+}} xmm2 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
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; CHECK-NEXT: vpslld $31, %xmm2, %xmm2
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; CHECK-NEXT: vpinsrw $4, %r9d, %xmm1, %xmm1
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; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: vpinsrw $5, %eax, %xmm1, %xmm1
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; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: vpinsrw $6, %eax, %xmm1, %xmm1
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; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: vpinsrw $7, %eax, %xmm1, %xmm1
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; CHECK-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
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; CHECK-NEXT: vpslld $31, %xmm1, %xmm1
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; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
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; CHECK-NEXT: vmaskmovps %ymm0, %ymm1, (%rdi)
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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call void @llvm.masked.store.v9f32.p0v9f32(<9 x float> %value, <9 x float>* %addr, i32 4, <9 x i1>%mask)
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ret void
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}
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define void @mstore_split13(<13 x float> %value, <13 x float>* %addr, <13 x i1> %mask) {
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; CHECK-LABEL: mstore_split13:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vinsertps {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[2,3]
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; CHECK-NEXT: vinsertps {{.*#+}} xmm4 = xmm4[0,1],xmm6[0],xmm4[3]
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; CHECK-NEXT: vinsertps {{.*#+}} xmm4 = xmm4[0,1,2],xmm7[0]
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; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
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; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3]
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; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0]
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; CHECK-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0
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; CHECK-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; CHECK-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[2,3]
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; CHECK-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],mem[0],xmm1[3]
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; CHECK-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],mem[0]
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; CHECK-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
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; CHECK-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
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; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: vmovd %eax, %xmm2
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; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: vpinsrw $1, %eax, %xmm2, %xmm2
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; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: vpinsrw $2, %eax, %xmm2, %xmm2
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; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: vpinsrw $3, %eax, %xmm2, %xmm2
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; CHECK-NEXT: vpmovzxwd {{.*#+}} xmm3 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero
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; CHECK-NEXT: vpslld $31, %xmm3, %xmm3
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; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: vpinsrw $4, %eax, %xmm2, %xmm2
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; CHECK-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
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; CHECK-NEXT: vpslld $31, %xmm2, %xmm2
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; CHECK-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2
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; CHECK-NEXT: vmaskmovps %ymm1, %ymm2, 32(%rdi)
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; CHECK-NEXT: vmovd %esi, %xmm1
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; CHECK-NEXT: vpinsrw $1, %edx, %xmm1, %xmm1
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; CHECK-NEXT: vpinsrw $2, %ecx, %xmm1, %xmm1
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; CHECK-NEXT: vpinsrw $3, %r8d, %xmm1, %xmm1
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; CHECK-NEXT: vpmovzxwd {{.*#+}} xmm2 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
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; CHECK-NEXT: vpslld $31, %xmm2, %xmm2
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; CHECK-NEXT: vpinsrw $4, %r9d, %xmm1, %xmm1
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; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: vpinsrw $5, %eax, %xmm1, %xmm1
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; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: vpinsrw $6, %eax, %xmm1, %xmm1
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; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: vpinsrw $7, %eax, %xmm1, %xmm1
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; CHECK-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
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; CHECK-NEXT: vpslld $31, %xmm1, %xmm1
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; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
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; CHECK-NEXT: vmaskmovps %ymm0, %ymm1, (%rdi)
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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call void @llvm.masked.store.v13f32.p0v13f32(<13 x float> %value, <13 x float>* %addr, i32 4, <13 x i1>%mask)
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ret void
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}
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define void @mstore_split14(<14 x float> %value, <14 x float>* %addr, <14 x i1> %mask) {
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; CHECK-LABEL: mstore_split14:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vinsertps {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[2,3]
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; CHECK-NEXT: vinsertps {{.*#+}} xmm4 = xmm4[0,1],xmm6[0],xmm4[3]
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; CHECK-NEXT: vinsertps {{.*#+}} xmm4 = xmm4[0,1,2],xmm7[0]
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; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
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; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3]
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; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0]
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; CHECK-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0
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; CHECK-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; CHECK-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[2,3]
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; CHECK-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],mem[0],xmm1[3]
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; CHECK-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],mem[0]
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; CHECK-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
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; CHECK-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],mem[0],xmm2[2,3]
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; CHECK-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
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; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: vmovd %eax, %xmm2
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; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: vpinsrw $1, %eax, %xmm2, %xmm2
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; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: vpinsrw $2, %eax, %xmm2, %xmm2
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; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: vpinsrw $3, %eax, %xmm2, %xmm2
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; CHECK-NEXT: vpmovzxwd {{.*#+}} xmm3 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero
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; CHECK-NEXT: vpslld $31, %xmm3, %xmm3
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; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: vpinsrw $4, %eax, %xmm2, %xmm2
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; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: vpinsrw $5, %eax, %xmm2, %xmm2
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; CHECK-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
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; CHECK-NEXT: vpslld $31, %xmm2, %xmm2
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; CHECK-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2
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; CHECK-NEXT: vmaskmovps %ymm1, %ymm2, 32(%rdi)
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; CHECK-NEXT: vmovd %esi, %xmm1
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; CHECK-NEXT: vpinsrw $1, %edx, %xmm1, %xmm1
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; CHECK-NEXT: vpinsrw $2, %ecx, %xmm1, %xmm1
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; CHECK-NEXT: vpinsrw $3, %r8d, %xmm1, %xmm1
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; CHECK-NEXT: vpmovzxwd {{.*#+}} xmm2 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
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; CHECK-NEXT: vpslld $31, %xmm2, %xmm2
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; CHECK-NEXT: vpinsrw $4, %r9d, %xmm1, %xmm1
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; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: vpinsrw $5, %eax, %xmm1, %xmm1
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; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: vpinsrw $6, %eax, %xmm1, %xmm1
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; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: vpinsrw $7, %eax, %xmm1, %xmm1
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; CHECK-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
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; CHECK-NEXT: vpslld $31, %xmm1, %xmm1
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; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
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; CHECK-NEXT: vmaskmovps %ymm0, %ymm1, (%rdi)
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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call void @llvm.masked.store.v14f32.p0v14f32(<14 x float> %value, <14 x float>* %addr, i32 4, <14 x i1>%mask)
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ret void
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}
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define void @mstore_split17(<17 x float> %value, <17 x float>* %addr, <17 x i1> %mask) {
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; CHECK-LABEL: mstore_split17:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vinsertps {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[2,3]
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||||||
|
; CHECK-NEXT: vinsertps {{.*#+}} xmm4 = xmm4[0,1],xmm6[0],xmm4[3]
|
||||||
|
; CHECK-NEXT: vinsertps {{.*#+}} xmm4 = xmm4[0,1,2],xmm7[0]
|
||||||
|
; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
|
||||||
|
; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3]
|
||||||
|
; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0]
|
||||||
|
; CHECK-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0
|
||||||
|
; CHECK-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
|
||||||
|
; CHECK-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[2,3]
|
||||||
|
; CHECK-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],mem[0],xmm1[3]
|
||||||
|
; CHECK-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],mem[0]
|
||||||
|
; CHECK-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
|
||||||
|
; CHECK-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],mem[0],xmm2[2,3]
|
||||||
|
; CHECK-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3]
|
||||||
|
; CHECK-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],mem[0]
|
||||||
|
; CHECK-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
|
||||||
|
; CHECK-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
|
||||||
|
; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
|
||||||
|
; CHECK-NEXT: vmovd %eax, %xmm3
|
||||||
|
; CHECK-NEXT: vpmovzxwd {{.*#+}} xmm3 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero
|
||||||
|
; CHECK-NEXT: vpslld $31, %xmm3, %xmm3
|
||||||
|
; CHECK-NEXT: vmaskmovps %ymm2, %ymm3, 64(%rdi)
|
||||||
|
; CHECK-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero
|
||||||
|
; CHECK-NEXT: vpinsrb $2, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
||||||
|
; CHECK-NEXT: vpinsrb $4, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
||||||
|
; CHECK-NEXT: vpinsrb $6, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
||||||
|
; CHECK-NEXT: vpmovzxwd {{.*#+}} xmm3 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero
|
||||||
|
; CHECK-NEXT: vpslld $31, %xmm3, %xmm3
|
||||||
|
; CHECK-NEXT: vpinsrb $8, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
||||||
|
; CHECK-NEXT: vpinsrb $10, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
||||||
|
; CHECK-NEXT: vpinsrb $12, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
||||||
|
; CHECK-NEXT: vpinsrb $14, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
||||||
|
; CHECK-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
|
||||||
|
; CHECK-NEXT: vpslld $31, %xmm2, %xmm2
|
||||||
|
; CHECK-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2
|
||||||
|
; CHECK-NEXT: vmaskmovps %ymm1, %ymm2, 32(%rdi)
|
||||||
|
; CHECK-NEXT: vmovd %esi, %xmm1
|
||||||
|
; CHECK-NEXT: vpinsrb $2, %edx, %xmm1, %xmm1
|
||||||
|
; CHECK-NEXT: vpinsrb $4, %ecx, %xmm1, %xmm1
|
||||||
|
; CHECK-NEXT: vpinsrb $6, %r8d, %xmm1, %xmm1
|
||||||
|
; CHECK-NEXT: vpmovzxwd {{.*#+}} xmm2 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
|
||||||
|
; CHECK-NEXT: vpslld $31, %xmm2, %xmm2
|
||||||
|
; CHECK-NEXT: vpinsrb $8, %r9d, %xmm1, %xmm1
|
||||||
|
; CHECK-NEXT: vpinsrb $10, {{[0-9]+}}(%rsp), %xmm1, %xmm1
|
||||||
|
; CHECK-NEXT: vpinsrb $12, {{[0-9]+}}(%rsp), %xmm1, %xmm1
|
||||||
|
; CHECK-NEXT: vpinsrb $14, {{[0-9]+}}(%rsp), %xmm1, %xmm1
|
||||||
|
; CHECK-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
|
||||||
|
; CHECK-NEXT: vpslld $31, %xmm1, %xmm1
|
||||||
|
; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
|
||||||
|
; CHECK-NEXT: vmaskmovps %ymm0, %ymm1, (%rdi)
|
||||||
|
; CHECK-NEXT: vzeroupper
|
||||||
|
; CHECK-NEXT: retq
|
||||||
|
call void @llvm.masked.store.v17f32.p0v17f32(<17 x float> %value, <17 x float>* %addr, i32 4, <17 x i1>%mask)
|
||||||
|
ret void
|
||||||
|
}
|
||||||
|
|
||||||
|
define void @mstore_split23(<23 x float> %value, <23 x float>* %addr, <23 x i1> %mask) {
|
||||||
|
; CHECK-LABEL: mstore_split23:
|
||||||
|
; CHECK: # %bb.0:
|
||||||
|
; CHECK-NEXT: vinsertps {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[2,3]
|
||||||
|
; CHECK-NEXT: vinsertps {{.*#+}} xmm4 = xmm4[0,1],xmm6[0],xmm4[3]
|
||||||
|
; CHECK-NEXT: vinsertps {{.*#+}} xmm4 = xmm4[0,1,2],xmm7[0]
|
||||||
|
; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
|
||||||
|
; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3]
|
||||||
|
; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0]
|
||||||
|
; CHECK-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0
|
||||||
|
; CHECK-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
|
||||||
|
; CHECK-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[2,3]
|
||||||
|
; CHECK-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],mem[0],xmm1[3]
|
||||||
|
; CHECK-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],mem[0]
|
||||||
|
; CHECK-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
|
||||||
|
; CHECK-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],mem[0],xmm2[2,3]
|
||||||
|
; CHECK-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3]
|
||||||
|
; CHECK-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
|
||||||
|
; CHECK-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
|
||||||
|
; CHECK-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],mem[0],xmm2[2,3]
|
||||||
|
; CHECK-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3]
|
||||||
|
; CHECK-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],mem[0]
|
||||||
|
; CHECK-NEXT: vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero
|
||||||
|
; CHECK-NEXT: vinsertps {{.*#+}} xmm3 = xmm3[0],mem[0],xmm3[2,3]
|
||||||
|
; CHECK-NEXT: vinsertps {{.*#+}} xmm3 = xmm3[0,1],mem[0],xmm3[3]
|
||||||
|
; CHECK-NEXT: vinsertps {{.*#+}} xmm3 = xmm3[0,1,2],mem[0]
|
||||||
|
; CHECK-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm2
|
||||||
|
; CHECK-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
|
||||||
|
; CHECK-NEXT: vmovd {{.*#+}} xmm3 = mem[0],zero,zero,zero
|
||||||
|
; CHECK-NEXT: vpinsrb $2, {{[0-9]+}}(%rsp), %xmm3, %xmm3
|
||||||
|
; CHECK-NEXT: vpinsrb $4, {{[0-9]+}}(%rsp), %xmm3, %xmm3
|
||||||
|
; CHECK-NEXT: vpinsrb $6, {{[0-9]+}}(%rsp), %xmm3, %xmm3
|
||||||
|
; CHECK-NEXT: vpmovzxwd {{.*#+}} xmm4 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero
|
||||||
|
; CHECK-NEXT: vpslld $31, %xmm4, %xmm4
|
||||||
|
; CHECK-NEXT: vpinsrb $8, {{[0-9]+}}(%rsp), %xmm3, %xmm3
|
||||||
|
; CHECK-NEXT: vpinsrb $10, {{[0-9]+}}(%rsp), %xmm3, %xmm3
|
||||||
|
; CHECK-NEXT: vpinsrb $12, {{[0-9]+}}(%rsp), %xmm3, %xmm3
|
||||||
|
; CHECK-NEXT: vpinsrb $14, {{[0-9]+}}(%rsp), %xmm3, %xmm3
|
||||||
|
; CHECK-NEXT: vpunpckhwd {{.*#+}} xmm3 = xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7]
|
||||||
|
; CHECK-NEXT: vpslld $31, %xmm3, %xmm3
|
||||||
|
; CHECK-NEXT: vinsertf128 $1, %xmm3, %ymm4, %ymm3
|
||||||
|
; CHECK-NEXT: vmaskmovps %ymm2, %ymm3, 32(%rdi)
|
||||||
|
; CHECK-NEXT: vmovd %eax, %xmm2
|
||||||
|
; CHECK-NEXT: vpinsrb $2, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
||||||
|
; CHECK-NEXT: vpinsrb $4, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
||||||
|
; CHECK-NEXT: vpinsrb $6, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
||||||
|
; CHECK-NEXT: vpmovzxwd {{.*#+}} xmm3 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero
|
||||||
|
; CHECK-NEXT: vpslld $31, %xmm3, %xmm3
|
||||||
|
; CHECK-NEXT: vpinsrb $8, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
||||||
|
; CHECK-NEXT: vpinsrb $10, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
||||||
|
; CHECK-NEXT: vpinsrb $12, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
||||||
|
; CHECK-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
|
||||||
|
; CHECK-NEXT: vpslld $31, %xmm2, %xmm2
|
||||||
|
; CHECK-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2
|
||||||
|
; CHECK-NEXT: vmaskmovps %ymm1, %ymm2, 64(%rdi)
|
||||||
|
; CHECK-NEXT: vmovd %esi, %xmm1
|
||||||
|
; CHECK-NEXT: vpinsrb $2, %edx, %xmm1, %xmm1
|
||||||
|
; CHECK-NEXT: vpinsrb $4, %ecx, %xmm1, %xmm1
|
||||||
|
; CHECK-NEXT: vpinsrb $6, %r8d, %xmm1, %xmm1
|
||||||
|
; CHECK-NEXT: vpmovzxwd {{.*#+}} xmm2 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
|
||||||
|
; CHECK-NEXT: vpslld $31, %xmm2, %xmm2
|
||||||
|
; CHECK-NEXT: vpinsrb $8, %r9d, %xmm1, %xmm1
|
||||||
|
; CHECK-NEXT: vpinsrb $10, {{[0-9]+}}(%rsp), %xmm1, %xmm1
|
||||||
|
; CHECK-NEXT: vpinsrb $12, {{[0-9]+}}(%rsp), %xmm1, %xmm1
|
||||||
|
; CHECK-NEXT: vpinsrb $14, {{[0-9]+}}(%rsp), %xmm1, %xmm1
|
||||||
|
; CHECK-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
|
||||||
|
; CHECK-NEXT: vpslld $31, %xmm1, %xmm1
|
||||||
|
; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
|
||||||
|
; CHECK-NEXT: vmaskmovps %ymm0, %ymm1, (%rdi)
|
||||||
|
; CHECK-NEXT: vzeroupper
|
||||||
|
; CHECK-NEXT: retq
|
||||||
|
call void @llvm.masked.store.v23f32.p0v23f32(<23 x float> %value, <23 x float>* %addr, i32 4, <23 x i1>%mask)
|
||||||
|
ret void
|
||||||
|
}
|
||||||
|
|
||||||
|
declare void @llvm.masked.store.v9f32.p0v9f32(<9 x float>, <9 x float>*, i32, <9 x i1>)
|
||||||
|
declare void @llvm.masked.store.v13f32.p0v13f32(<13 x float>, <13 x float>*, i32, <13 x i1>)
|
||||||
|
declare void @llvm.masked.store.v14f32.p0v14f32(<14 x float>, <14 x float>*, i32, <14 x i1>)
|
||||||
|
declare void @llvm.masked.store.v17f32.p0v17f32(<17 x float>, <17 x float>*, i32, <17 x i1>)
|
||||||
|
declare void @llvm.masked.store.v23f32.p0v23f32(<23 x float>, <23 x float>*, i32, <23 x i1>)
|
||||||
Loading…
Reference in New Issue