forked from OSchip/llvm-project
AMDGPU: Do not combine loads/store across physreg defs
Summary:
Since this pass operates on machine SSA form, this should only really
affect M0 in practice.
Fixes various piglit variable-indexing/vs-varying-array-mat4-index-*
Change-Id: Ib2a1dc3a8d7b08225a8da49a86f533faa0986aa8
Fixes: r317751 ("AMDGPU: Merge S_BUFFER_LOAD_DWORD_IMM into x2, x4")
Reviewers: arsenm, mareko, rampitec
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D40343
llvm-svn: 325677
This commit is contained in:
Nicolai Haehnle
parent
d6e1a9404d
commit
770397f4cd
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@ -228,6 +228,16 @@ canMoveInstsAcrossMemOp(MachineInstr &MemOp,
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return true;
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}
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static bool
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hasPhysRegDef(MachineInstr &MI) {
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for (const MachineOperand &Def : MI.defs()) {
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if (Def.isReg() &&
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TargetRegisterInfo::isPhysicalRegister(Def.getReg()))
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return true;
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}
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return false;
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}
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bool SILoadStoreOptimizer::offsetsCanBeCombined(CombineInfo &CI) {
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// XXX - Would the same offset be OK? Is there any reason this would happen or
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// be useful?
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@ -350,6 +360,13 @@ bool SILoadStoreOptimizer::findMatchingInst(CombineInfo &CI) {
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return false;
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}
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if (hasPhysRegDef(*MBBI)) {
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// We could re-order this instruction in theory, but it would require
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// tracking physreg defs and uses. This should only affect M0 in
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// practice.
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return false;
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}
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if (MBBI->mayLoadOrStore() &&
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(!memAccessesCanBeReordered(*CI.I, *MBBI, TII, AA) ||
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!canMoveInstsAcrossMemOp(*MBBI, CI.InstsToMove, TII, AA))) {
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@ -437,7 +454,8 @@ bool SILoadStoreOptimizer::findMatchingInst(CombineInfo &CI) {
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// down past this instruction.
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// check if we can move I across MBBI and if we can move all I's users
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if (!memAccessesCanBeReordered(*CI.I, *MBBI, TII, AA) ||
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!canMoveInstsAcrossMemOp(*MBBI, CI.InstsToMove, TII, AA))
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!canMoveInstsAcrossMemOp(*MBBI, CI.InstsToMove, TII, AA) ||
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hasPhysRegDef(*MBBI))
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break;
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}
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return false;
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@ -613,6 +613,24 @@ bb:
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ret void
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}
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; GCN-LABEL: ds_read_call_read:
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; GCN: ds_read_b32
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; GCN: s_swappc_b64
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; GCN: ds_read_b32
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define amdgpu_kernel void @ds_read_call_read(i32 addrspace(1)* %out, i32 addrspace(3)* %arg) {
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%x = call i32 @llvm.amdgcn.workitem.id.x()
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%arrayidx0 = getelementptr i32, i32 addrspace(3)* %arg, i32 %x
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%arrayidx1 = getelementptr i32, i32 addrspace(3)* %arrayidx0, i32 1
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%v0 = load i32, i32 addrspace(3)* %arrayidx0, align 4
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call void @void_func_void()
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%v1 = load i32, i32 addrspace(3)* %arrayidx1, align 4
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%r = add i32 %v0, %v1
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store i32 %r, i32 addrspace(1)* %out, align 4
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ret void
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}
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declare void @void_func_void() #3
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declare i32 @llvm.amdgcn.workgroup.id.x() #1
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declare i32 @llvm.amdgcn.workgroup.id.y() #1
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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@ -623,3 +641,4 @@ declare void @llvm.amdgcn.s.barrier() #2
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone speculatable }
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attributes #2 = { convergent nounwind }
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attributes #3 = { nounwind noinline }
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@ -160,21 +160,25 @@ bb:
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; SI won't merge ds memory operations, because of the signed offset bug, so
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; we only have check lines for VI.
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; VI-LABEL: v_interp_readnone:
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; VI: s_mov_b32 m0, 0
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; VI-DAG: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0
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; VI-DAG: v_interp_mov_f32 v{{[0-9]+}}, p0, attr0.x{{$}}
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; VI: s_mov_b32 m0, -1{{$}}
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; VI: ds_write2_b32 v{{[0-9]+}}, [[ZERO]], [[ZERO]] offset1:4
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define amdgpu_ps void @v_interp_readnone(float addrspace(3)* %lds) #0 {
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bb:
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store float 0.000000e+00, float addrspace(3)* %lds
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%tmp1 = call float @llvm.amdgcn.interp.mov(i32 2, i32 0, i32 0, i32 0)
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%tmp2 = getelementptr float, float addrspace(3)* %lds, i32 4
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store float 0.000000e+00, float addrspace(3)* %tmp2
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp1, float %tmp1, float %tmp1, float %tmp1, i1 true, i1 true) #0
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ret void
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}
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;
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; TODO: VI won't merge them either, because we are conservative about moving
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; instructions past changes to physregs.
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;
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; TODO-VI-LABEL: v_interp_readnone:
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; TODO-VI: s_mov_b32 m0, 0
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; TODO-VI-DAG: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0
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; TODO-VI-DAG: v_interp_mov_f32 v{{[0-9]+}}, p0, attr0.x{{$}}
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; TODO-VI: s_mov_b32 m0, -1{{$}}
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; TODO-VI: ds_write2_b32 v{{[0-9]+}}, [[ZERO]], [[ZERO]] offset1:4
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;define amdgpu_ps void @v_interp_readnone(float addrspace(3)* %lds) #0 {
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;bb:
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; store float 0.000000e+00, float addrspace(3)* %lds
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; %tmp1 = call float @llvm.amdgcn.interp.mov(i32 2, i32 0, i32 0, i32 0)
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; %tmp2 = getelementptr float, float addrspace(3)* %lds, i32 4
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; store float 0.000000e+00, float addrspace(3)* %tmp2
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; call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp1, float %tmp1, float %tmp1, float %tmp1, i1 true, i1 true) #0
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; ret void
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;}
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; Thest that v_interp_p1 uses different source and destination registers
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; on 16 bank LDS chips.
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@ -232,6 +232,48 @@ main_body:
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ret void
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}
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; GCN-LABEL: {{^}}smrd_imm_nomerge_m0:
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;
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; In principle we could merge the loads here as well, but it would require
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; careful tracking of physical registers since both v_interp* and v_movrel*
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; instructions (or gpr idx mode) use M0.
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;
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; GCN: s_buffer_load_dword
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; GCN: s_buffer_load_dword
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define amdgpu_ps float @smrd_imm_nomerge_m0(<4 x i32> inreg %desc, i32 inreg %prim, float %u, float %v) #0 {
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main_body:
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%idx1.f = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 0)
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%idx1 = bitcast float %idx1.f to i32
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%v0.x1 = call nsz float @llvm.amdgcn.interp.p1(float %u, i32 0, i32 0, i32 %prim)
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%v0.x = call nsz float @llvm.amdgcn.interp.p2(float %v0.x1, float %v, i32 0, i32 0, i32 %prim)
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%v0.y1 = call nsz float @llvm.amdgcn.interp.p1(float %u, i32 0, i32 1, i32 %prim)
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%v0.y = call nsz float @llvm.amdgcn.interp.p2(float %v0.y1, float %v, i32 0, i32 1, i32 %prim)
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%v0.z1 = call nsz float @llvm.amdgcn.interp.p1(float %u, i32 0, i32 2, i32 %prim)
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%v0.z = call nsz float @llvm.amdgcn.interp.p2(float %v0.z1, float %v, i32 0, i32 2, i32 %prim)
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%v0.tmp0 = insertelement <3 x float> undef, float %v0.x, i32 0
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%v0.tmp1 = insertelement <3 x float> %v0.tmp0, float %v0.y, i32 1
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%v0 = insertelement <3 x float> %v0.tmp1, float %v0.z, i32 2
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%a = extractelement <3 x float> %v0, i32 %idx1
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%v1.x1 = call nsz float @llvm.amdgcn.interp.p1(float %u, i32 1, i32 0, i32 %prim)
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%v1.x = call nsz float @llvm.amdgcn.interp.p2(float %v1.x1, float %v, i32 1, i32 0, i32 %prim)
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%v1.y1 = call nsz float @llvm.amdgcn.interp.p1(float %u, i32 1, i32 1, i32 %prim)
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%v1.y = call nsz float @llvm.amdgcn.interp.p2(float %v1.y1, float %v, i32 1, i32 1, i32 %prim)
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%v1.z1 = call nsz float @llvm.amdgcn.interp.p1(float %u, i32 1, i32 2, i32 %prim)
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%v1.z = call nsz float @llvm.amdgcn.interp.p2(float %v1.z1, float %v, i32 1, i32 2, i32 %prim)
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%v1.tmp0 = insertelement <3 x float> undef, float %v0.x, i32 0
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%v1.tmp1 = insertelement <3 x float> %v0.tmp0, float %v0.y, i32 1
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%v1 = insertelement <3 x float> %v0.tmp1, float %v0.z, i32 2
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%b = extractelement <3 x float> %v1, i32 %idx1
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%c = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 4)
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%res.tmp = fadd float %a, %b
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%res = fadd float %res.tmp, %c
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ret float %res
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}
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; GCN-LABEL: {{^}}smrd_vgpr_merged:
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; GCN-NEXT: %bb.
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; GCN-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4
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@ -289,8 +331,11 @@ ret_block: ; preds = %.outer, %.label22, %
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declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0
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declare float @llvm.SI.load.const.v4i32(<4 x i32>, i32) #1
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declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #2
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declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #2
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind readnone speculatable }
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!0 = !{}
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