forked from OSchip/llvm-project
ARM sched model: Add branch thumb instructions
llvm-svn: 183265
This commit is contained in:
Arnold Schwaighofer
parent
17359d9ba2
commit
76e2394799
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@ -395,7 +395,7 @@ def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,
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// Indirect branches
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let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
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def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
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T1Special<{1,1,0,?}> {
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T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
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// A6.2.3 & A8.6.25
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bits<4> Rm;
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let Inst{6-3} = Rm;
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@ -406,12 +406,12 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
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let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
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def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br,
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[(ARMretflag)], (tBX LR, pred:$p)>;
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[(ARMretflag)], (tBX LR, pred:$p)>, Sched<[WriteBr]>;
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// Alternative return instruction used by vararg functions.
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def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p),
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2, IIC_Br, [],
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(tBX GPR:$Rm, pred:$p)>;
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(tBX GPR:$Rm, pred:$p)>, Sched<[WriteBr]>;
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}
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// All calls clobber the non-callee saved registers. SP is marked as a use to
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@ -424,7 +424,7 @@ let isCall = 1,
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(outs), (ins pred:$p, t_bltarget:$func), IIC_Br,
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"bl${p}\t$func",
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[(ARMtcall tglobaladdr:$func)]>,
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Requires<[IsThumb]> {
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Requires<[IsThumb]>, Sched<[WriteBrL]> {
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bits<24> func;
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let Inst{26} = func{23};
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let Inst{25-16} = func{20-11};
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@ -438,7 +438,7 @@ let isCall = 1,
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(outs), (ins pred:$p, t_blxtarget:$func), IIC_Br,
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"blx${p}\t$func",
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[(ARMcall tglobaladdr:$func)]>,
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Requires<[IsThumb, HasV5T]> {
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Requires<[IsThumb, HasV5T]>, Sched<[WriteBrL]> {
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bits<24> func;
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let Inst{26} = func{23};
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let Inst{25-16} = func{20-11};
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@ -453,7 +453,7 @@ let isCall = 1,
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"blx${p}\t$func",
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[(ARMtcall GPR:$func)]>,
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Requires<[IsThumb, HasV5T]>,
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T1Special<{1,1,1,?}> { // A6.2.3 & A8.6.24;
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T1Special<{1,1,1,?}>, Sched<[WriteBrL]> { // A6.2.3 & A8.6.24;
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bits<4> func;
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let Inst{6-3} = func;
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let Inst{2-0} = 0b000;
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@ -463,14 +463,14 @@ let isCall = 1,
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def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func),
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4, IIC_Br,
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[(ARMcall_nolink tGPR:$func)]>,
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Requires<[IsThumb, IsThumb1Only]>;
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Requires<[IsThumb, IsThumb1Only]>, Sched<[WriteBr]>;
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}
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let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
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let isPredicable = 1 in
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def tB : T1pI<(outs), (ins t_brtarget:$target), IIC_Br,
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"b", "\t$target", [(br bb:$target)]>,
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T1Encoding<{1,1,1,0,0,?}> {
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T1Encoding<{1,1,1,0,0,?}>, Sched<[WriteBr]> {
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bits<11> target;
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let Inst{10-0} = target;
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}
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@ -480,12 +480,14 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
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// the clobber of LR.
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let Defs = [LR] in
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def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target, pred:$p),
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4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>;
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4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>,
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Sched<[WriteBrTbl]>;
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def tBR_JTr : tPseudoInst<(outs),
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(ins tGPR:$target, i32imm:$jt, i32imm:$id),
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0, IIC_Br,
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[(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> {
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[(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>,
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Sched<[WriteBrTbl]> {
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list<Predicate> Predicates = [IsThumb, IsThumb1Only];
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}
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}
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@ -496,7 +498,7 @@ let isBranch = 1, isTerminator = 1 in
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def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br,
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"b${p}\t$target",
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[/*(ARMbrcond bb:$target, imm:$cc)*/]>,
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T1BranchCond<{1,1,0,1}> {
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T1BranchCond<{1,1,0,1}>, Sched<[WriteBr]> {
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bits<4> p;
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bits<8> target;
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let Inst{11-8} = p;
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@ -510,7 +512,7 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
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def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst),
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4, IIC_Br, [],
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(tBX GPR:$dst, (ops 14, zero_reg))>,
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Requires<[IsThumb]>;
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Requires<[IsThumb]>, Sched<[WriteBr]>;
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}
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// tTAILJMPd: IOS version uses a Thumb2 branch (no Thumb1 tail calls
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// on IOS), so it's in ARMInstrThumb2.td.
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@ -520,7 +522,7 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
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(ins t_brtarget:$dst, pred:$p),
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4, IIC_Br, [],
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(tB t_brtarget:$dst, pred:$p)>,
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Requires<[IsThumb, IsNotIOS]>;
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Requires<[IsThumb, IsNotIOS]>, Sched<[WriteBr]>;
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}
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}
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@ -530,7 +532,7 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
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// If Inst{11-8} == 0b1111 then SEE SVC
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let isCall = 1, Uses = [SP] in
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def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br,
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"svc", "\t$imm", []>, Encoding16 {
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"svc", "\t$imm", []>, Encoding16, Sched<[WriteBr]> {
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bits<8> imm;
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let Inst{15-12} = 0b1101;
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let Inst{11-8} = 0b1111;
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@ -540,7 +542,7 @@ def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br,
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// The assembler uses 0xDEFE for a trap instruction.
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let isBarrier = 1, isTerminator = 1 in
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def tTRAP : TI<(outs), (ins), IIC_Br,
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"trap", [(trap)]>, Encoding16 {
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"trap", [(trap)]>, Encoding16, Sched<[WriteBr]> {
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let Inst = 0xdefe;
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}
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@ -1230,7 +1232,8 @@ def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
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// complete with fixup for the aeabi_read_tp function.
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let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in
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def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br,
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[(set R0, ARMthread_pointer)]>;
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[(set R0, ARMthread_pointer)]>,
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Sched<[WriteBr]>;
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//===----------------------------------------------------------------------===//
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// SJLJ Exception handling intrinsics
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@ -1396,13 +1399,13 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
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hasExtraDefRegAllocReq = 1 in
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def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
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2, IIC_iPop_Br, [],
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(tPOP pred:$p, reglist:$regs)>;
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(tPOP pred:$p, reglist:$regs)>, Sched<[WriteBrL]>;
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// Indirect branch using "mov pc, $Rm"
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let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
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def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p),
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2, IIC_Br, [(brind GPR:$Rm)],
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(tMOVr PC, GPR:$Rm, pred:$p)>;
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(tMOVr PC, GPR:$Rm, pred:$p)>, Sched<[WriteBr]>;
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}
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