forked from OSchip/llvm-project
parent
2d48f6537d
commit
76d51c6c89
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@ -2775,7 +2775,6 @@ SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
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SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
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ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N);
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EVT VT = N->getValueType(0);
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DebugLoc dl = N->getDebugLoc();
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@ -2838,13 +2837,12 @@ SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
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EVT NOutVTElem = NOutVT.getVectorElementType();
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DebugLoc dl = N->getDebugLoc();
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SDValue ConvertedVector = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
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N->getOperand(0));
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SDValue V0 = GetPromotedInteger(N->getOperand(0));
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SDValue ConvertedVector = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, V0);
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SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl,
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NOutVTElem, N->getOperand(1));
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return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,NOutVT,
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return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT,
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ConvertedVector, ConvElem, N->getOperand(2));
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}
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@ -2860,15 +2858,16 @@ SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) {
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}
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SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
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DebugLoc dl = N->getDebugLoc();
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unsigned NumElems = N->getNumOperands();
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EVT RetSclrTy = N->getValueType(0).getVectorElementType();
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SmallVector<SDValue, 8> NewOps;
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NewOps.reserve(NumElems);
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// For each incoming vector
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for (unsigned VecIdx = 0, E = N->getNumOperands(); VecIdx!= E; ++VecIdx) {
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for (unsigned VecIdx = 0; VecIdx != NumElems; ++VecIdx) {
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SDValue Incoming = GetPromotedInteger(N->getOperand(VecIdx));
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EVT SclrTy = Incoming->getValueType(0).getVectorElementType();
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unsigned NumElem = Incoming->getValueType(0).getVectorNumElements();
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